| Line 59... |
Line 59... |
input i_decode_daccess, // Indicates a data access
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input i_decode_daccess, // Indicates a data access
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input [7:0] i_decode_load_rd, // The destination register for a load instruction
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input [7:0] i_decode_load_rd, // The destination register for a load instruction
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output reg [31:0] o_copro_write_data = 'd0,
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output reg [31:0] o_copro_write_data = 'd0,
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output reg [31:0] o_write_data = 'd0,
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output reg [31:0] o_write_data = 'd0,
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output reg [31:0] o_iaddress = 32'hdead_dead,
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output wire [31:0] o_iaddress,
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output [31:0] o_iaddress_nxt, // un-registered version of address to the
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output [31:0] o_iaddress_nxt, // un-registered version of address to the
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// cache rams address ports
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// cache rams address ports
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output reg o_iaddress_valid = 'd0, // High when instruction address is valid
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output reg o_iaddress_valid = 'd0, // High when instruction address is valid
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output reg [31:0] o_daddress = 32'h0, // Address to data cache
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output reg [31:0] o_daddress = 32'h0, // Address to data cache
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output [31:0] o_daddress_nxt, // un-registered version of address to the
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output [31:0] o_daddress_nxt, // un-registered version of address to the
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| Line 215... |
Line 215... |
wire ldm_flags;
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wire ldm_flags;
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wire ldm_status_bits;
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wire ldm_status_bits;
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wire carry_in;
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wire carry_in;
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reg [31:0] iaddress_r = 32'hdead_dead;
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// ========================================================
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// ========================================================
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// Status Bits in PC register
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// Status Bits in PC register
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// ========================================================
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// ========================================================
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wire [1:0] status_bits_mode_out;
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wire [1:0] status_bits_mode_out;
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Line 546... |
o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged;
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o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged;
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o_exclusive <= exclusive_update ? i_decode_exclusive : o_exclusive;
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o_exclusive <= exclusive_update ? i_decode_exclusive : o_exclusive;
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o_write_enable <= write_enable_update ? write_enable_nxt : o_write_enable;
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o_write_enable <= write_enable_update ? write_enable_nxt : o_write_enable;
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o_write_data <= write_data_update ? write_data_nxt : o_write_data;
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o_write_data <= write_data_update ? write_data_nxt : o_write_data;
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o_byte_enable <= byte_enable_update ? byte_enable_nxt : o_byte_enable;
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o_byte_enable <= byte_enable_update ? byte_enable_nxt : o_byte_enable;
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o_iaddress <= iaddress_update ? o_iaddress_nxt : o_iaddress;
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iaddress_r <= iaddress_update ? o_iaddress_nxt : iaddress_r;
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o_iaddress_valid <= iaddress_update ? iaddress_valid_nxt : o_iaddress_valid;
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o_iaddress_valid <= iaddress_update ? iaddress_valid_nxt : o_iaddress_valid;
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o_adex <= iaddress_update ? adex_nxt : o_adex;
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o_adex <= iaddress_update ? adex_nxt : o_adex;
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o_copro_write_data <= copro_write_data_update ? write_data_nxt : o_copro_write_data;
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o_copro_write_data <= copro_write_data_update ? write_data_nxt : o_copro_write_data;
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base_address <= base_address_update ? rn : base_address;
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base_address <= base_address_update ? rn : base_address;
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Line 560... |
status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt : status_bits_mode_rds_oh;
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status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt : status_bits_mode_rds_oh;
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status_bits_irq_mask <= status_bits_irq_mask_update ? status_bits_irq_mask_nxt : status_bits_irq_mask;
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status_bits_irq_mask <= status_bits_irq_mask_update ? status_bits_irq_mask_nxt : status_bits_irq_mask;
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status_bits_firq_mask <= status_bits_firq_mask_update ? status_bits_firq_mask_nxt : status_bits_firq_mask;
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status_bits_firq_mask <= status_bits_firq_mask_update ? status_bits_firq_mask_nxt : status_bits_firq_mask;
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end
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end
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assign o_iaddress = iaddress_r;
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// ========================================================
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// ========================================================
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// Instantiate Barrel Shift
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// Instantiate Barrel Shift
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// ========================================================
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// ========================================================
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assign carry_in = i_use_carry_in ? status_bits_flags[1] : 1'd0;
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assign carry_in = i_use_carry_in ? status_bits_flags[1] : 1'd0;
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