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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_mem.v] - Diff between revs 60 and 82
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Rev 82 |
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Line 76... |
input [127:0] i_wb_cached_rdata, // wb bus
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input [127:0] i_wb_cached_rdata, // wb bus
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input i_wb_cached_ready, // wishbone access complete and read data valid
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input i_wb_cached_ready, // wishbone access complete and read data valid
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input i_wb_uncached_ready // wishbone access complete and read data valid
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input i_wb_uncached_ready // wishbone access complete and read data valid
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);
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);
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`include "memory_configuration.v"
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`include "memory_configuration.vh"
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wire [31:0] cache_read_data;
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wire [31:0] cache_read_data;
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wire address_cachable;
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wire address_cachable;
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wire sel_cache_p;
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wire sel_cache_p;
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wire sel_cache;
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wire sel_cache;
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