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`#######################################################################`	`#######################################################################`
`## File: mor1k_mpsoc.MPSOC`	`## File: mor1k_mpsoc.MPSOC`
`##`	`##`
`## Copyright (C) 2014-2019 Alireza Monemi`	`## Copyright (C) 2014-2021 Alireza Monemi`
`##`	`##`
`## This file is part of ProNoC 1.9.1`	`## This file is part of ProNoC 2.1.0`
`##`	`##`
`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`	`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
`## MAY CAUSE UNEXPECTED BEHAVIOR.`	`## MAY CAUSE UNEXPECTED BEHAVIOR.`
`################################################################################`	`################################################################################`

`$mor1k_mpsoc = bless( {`	`$mor1k_mpsoc = bless( {`
`'RAM3' => {`	`'noc_type' => {`
	`'ROUTER_TYPE' => '"VC_BASED"'`
	`},`
	`'compile_pin_pos' => {`
	`'processors_en' => [`
	`6,`
	`0`
	`],`
	`'TOP_reset' => [`
	`0,`
	`0`
	`],`
	`'jtag_debug_reset_in' => [`
	`0,`
	`0`
	`],`
	`'TOP_clk' => [`
	`4,`
	`0`
	`]`
	`},`
	`'MEM2' => {`
	`'width' => '14',`
	`'percent' => '75'`
	`},`
	`'RAM2' => {`
`'end' => 65536,`	`'end' => 65536,`
`'start' => 49152`	`'start' => 49152`
`},`	`},`
`'mpsoc_name' => 'mor1k_mpsoc',`
`'compile_pin_range_lsb' => {`
`'processors_en' => 0`
`},`
`'ROM3' => {`	`'ROM3' => {`
`'end' => 49152,`	`'end' => 49152,`
`'start' => 0`	`'start' => 0`
`},`	`},`
`'compile' => {`	`'noc_param' => {`
`'cpu_num' => '4',`	`'T2' => '2',`
`'modelsim_bin' => 'export LM_LICENSE_FILE=1717@epi03.bsc.es; /home/alireza/intelFPGA_lite/questa/questasim/bin',`	`'TOPOLOGY' => '"MESH"',`
`'type' => 'QuartusII',`	`'SELF_LOOP_EN' => '"NO"',`
`'compilers' => 'QuartusII,Vivado,Verilator,Modelsim',`	`'COMBINATION_TYPE' => '"COMB_NONSPEC"',`
`'board' => 'DE10_Nano_VB2',`	`'WEIGHTw' => '4',`
`'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin'`	`'BYTE_EN' => '1',`
	`'SMART_MAX' => '0',`
	`'FIRST_ARBITER_EXT_P_EN' => 1,`
	`'ESCAP_VC_MASK' => '2\'b01',`
	`'PCK_TYPE' => '"MULTI_FLIT"',`
	`'DEBUG_EN' => '0',`
	`'CONGESTION_INDEX' => 3,`
	`'T3' => '1',`
	`'MCAST_ENDP_LIST' => '\'hf',`
	`'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',`
	`'T1' => '2',`
	`'MIN_PCK_SIZE' => '2',`
	`'B' => '4',`
	`'MUX_TYPE' => '"BINARY"',`
	`'ROUTE_NAME' => '"XY"',`
	`'CAST_TYPE' => '"UNICAST"',`
	`'SWA_ARBITER_TYPE' => '"RRA"',`
	`'C' => 0,`
	`'Fpay' => '32',`
	`'V' => '2',`
	`'AVC_ATOMIC_EN' => 0,`
	`'LB' => '4',`
	`'VC_REALLOCATION_TYPE' => '"NONATOMIC"',`
	`'SSA_EN' => '"NO"'`
`},`	`},`
`'MEM2' => {`	`'compile_assign_type' => {`
`'percent' => '75',`	`'processors_en' => 'Direct',`
`'width' => '14'`	`'TOP_clk' => 'Direct',`
	`'jtag_debug_reset_in' => 'Direct',`
	`'TOP_reset' => 'Direct'`
`},`	`},`
	`'fpga_param' => {},`
`'socs' => {`	`'socs' => {`
`'mor1k_tile' => {`	`'mor1k_tile' => {`
`'tile_nums' => [`
`0,`
`1,`
`2,`
`3`
`],`
`'top' => bless( {`	`'top' => bless( {`
`'interface' => {`	`'parameters' => {`
`'socket:RxD_sim[0]' => {`	`'uart_JDw' => '32',`
`'ports' => {`	`'ram_JTAG_INDEX' => 'CORE_ID',`
`'uart_RxD_din_sim' => {`	`'uart_JAw' => '32',`
`'range' => '7:0 ',`	`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`
`'intfc_port' => 'RxD_din_sim',`	`'uart_JTAG_CHAIN' => '3',`
`'instance_name' => 'ProNoC_jtag_uart0',`	`'ram_JTAG_CHAIN' => '4',`
`'type' => 'input'`	`'ram_JDw' => 'ram_Dw',`
	`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
	`'uart_JTAG_INDEX' => '126-CORE_ID',`
	`'ram_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',`
	`'uart_JINDEXw' => '8',`
	`'uart_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',`
	`'ram_JINDEXw' => '8',`
	`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
	`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
	`'ram_Dw' => '32',`
	`'ram_JSTATUSw' => '8',`
	`'uart_JSTATUSw' => '8',`
	`'ram_JAw' => '32'`
`},`	`},`
`'uart_RxD_ready_sim' => {`	`'tiles' => {`
`'instance_name' => 'ProNoC_jtag_uart0',`	`'1' => {`
`'type' => 'output',`	`'parameters' => {`
`'intfc_port' => 'RxD_ready_sim',`	`'ram_JINDEXw' => '8',`
`'range' => ''`	`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
	`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
	`'ram_JSTATUSw' => '8',`
	`'uart_JSTATUSw' => '8',`
	`'ram_JAw' => '32',`
	`'ram_Dw' => '32',`
	`'uart_JAw' => '32',`
	`'ram_JTAG_INDEX' => 'CORE_ID',`
	`'uart_JDw' => '32',`
	`'ram_Aw' => '14',`
	`'ram_JTAG_CHAIN' => '4',`
	`'uart_JTAG_CHAIN' => '3',`
	`'ram_JDw' => 'ram_Dw',`
	`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`
	`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
	`'uart_JINDEXw' => '8',`
	`'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
	`'uart_JTAG_INDEX' => '126-CORE_ID',`
	`'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"'`
	`}`
`},`	`},`
`'uart_RxD_wr_sim' => {`	`'2' => {`
`'range' => '',`	`'parameters' => {`
`'type' => 'input',`	`'ram_JINDEXw' => '8',`
`'intfc_port' => 'RxD_wr_sim',`	`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
`'instance_name' => 'ProNoC_jtag_uart0'`	`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
	`'ram_JSTATUSw' => '8',`
	`'ram_JAw' => '32',`
	`'uart_JSTATUSw' => '8',`
	`'ram_Dw' => '32',`
	`'ram_JTAG_INDEX' => 'CORE_ID',`
	`'uart_JAw' => '32',`
	`'uart_JDw' => '32',`
	`'ram_Aw' => '14',`
	`'ram_JTAG_CHAIN' => '4',`
	`'uart_JTAG_CHAIN' => '3',`
	`'ram_JDw' => 'ram_Dw',`
	`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`
	`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
	`'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
	`'uart_JINDEXw' => '8',`
	`'uart_JTAG_INDEX' => '126-CORE_ID',`
	`'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"'`
`}`	`}`
	`},`
	`'0' => {`
	`'parameters' => {`
	`'ram_JINDEXw' => '8',`
	`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
	`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
	`'ram_Dw' => '32',`
	`'ram_JSTATUSw' => '8',`
	`'ram_JAw' => '32',`
	`'uart_JSTATUSw' => '8',`
	`'uart_JDw' => '32',`
	`'ram_Aw' => '14',`
	`'uart_JAw' => '32',`
	`'ram_JTAG_INDEX' => 'CORE_ID',`
	`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`
	`'uart_JTAG_CHAIN' => '3',`
	`'ram_JTAG_CHAIN' => '4',`
	`'ram_JDw' => 'ram_Dw',`
	`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
	`'uart_JTAG_INDEX' => '126-CORE_ID',`
	`'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
	`'uart_JINDEXw' => '8',`
	`'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"'`
`}`	`}`
`},`	`},`
`'plug:clk[0]' => {`	`'3' => {`
`'ports' => {`	`'parameters' => {`
`'source_clk_in' => {`	`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
`'range' => '',`	`'uart_JTAG_INDEX' => '126-CORE_ID',`
`'type' => 'input',`	`'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
`'instance_name' => 'clk_source0',`	`'uart_JINDEXw' => '8',`
`'intfc_port' => 'clk_i'`	`'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
	`'uart_JDw' => '32',`
	`'ram_Aw' => '14',`
	`'ram_JTAG_INDEX' => 'CORE_ID',`
	`'uart_JAw' => '32',`
	`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`
	`'ram_JTAG_CHAIN' => '4',`
	`'uart_JTAG_CHAIN' => '3',`
	`'ram_JDw' => 'ram_Dw',`
	`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
	`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
	`'ram_Dw' => '32',`
	`'ram_JSTATUSw' => '8',`
	`'ram_JAw' => '32',`
	`'uart_JSTATUSw' => '8',`
	`'ram_JINDEXw' => '8'`
`}`	`}`
`}`	`}`
`},`	`},`
`'plug:enable[0]' => {`	`'instance_ids' => {`
	`'mor1kx0' => {`
`'ports' => {`	`'ports' => {`
`'cpu_cpu_en' => {`	`'cpu_cpu_en' => {`
`'range' => '',`	`'range' => '',`
`'instance_name' => 'mor1kx0',`	`'intfc_name' => 'plug:enable[0]',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'enable_i'`	`'intfc_port' => 'enable_i'`
`}`	`}`
`}`
`},`	`},`
`'plug:reset[0]' => {`	`'module' => 'mor1kx',`
`'ports' => {`	`'instance' => 'cpu',`
`'source_reset_in' => {`	`'module_name' => 'mor1k',`
`'range' => '',`	`'category' => 'Processor',`
`'instance_name' => 'clk_source0',`	`'localparam' => {`
`'type' => 'input',`	`'cpu_FEATURE_IMMU' => {`
`'intfc_port' => 'reset_i'`	`'info' => '',`
`}`	`'default' => '"ENABLED"',`
`}`	`'redefine_param' => 1,`
	`'global_param' => 'Localparam',`
	`'content' => '"NONE","ENABLED"',`
	`'type' => 'Combo-box'`
`},`	`},`
`'socket:jtag_to_wb[0]' => {`	`'cpu_FEATURE_DIVIDER' => {`
`'ports' => {`	`'redefine_param' => 1,`
`'uart_jtag_to_wb' => {`	`'global_param' => 'Localparam',`
`'range' => 'uart_J2WBw-1 : 0',`	`'content' => '"SERIAL","NONE"',`
`'instance_name' => 'ProNoC_jtag_uart0',`	`'info' => 'Specify the divider implementation',`
`'type' => 'input',`	`'type' => 'Combo-box',`
`'intfc_port' => 'jwb_i'`	`'default' => '"SERIAL"'`
`},`	`},`
`'ram_jtag_to_wb' => {`	`'cpu_FEATURE_DMMU' => {`
`'range' => 'ram_J2WBw-1 : 0',`	`'info' => '',`
`'intfc_port' => 'jwb_i',`	`'default' => '"ENABLED"',`
`'instance_name' => 'single_port_ram0',`	`'redefine_param' => 1,`
`'type' => 'input'`	`'global_param' => 'Localparam',`
	`'content' => '"NONE","ENABLED"',`
	`'type' => 'Combo-box'`
`},`	`},`
`'uart_wb_to_jtag' => {`	`'cpu_OPTION_DCACHE_SNOOP' => {`
`'range' => 'uart_WB2Jw-1 : 0',`	`'global_param' => 'Localparam',`
`'type' => 'output',`	`'redefine_param' => 1,`
`'intfc_port' => 'jwb_o',`	`'type' => 'Combo-box',`
`'instance_name' => 'ProNoC_jtag_uart0'`	`'default' => '"ENABLED"',`
	`'info' => '',`
	`'content' => '"NONE","ENABLED"'`
`},`	`},`
`'ram_wb_to_jtag' => {`	`'cpu_FEATURE_MULTIPLIER' => {`
`'range' => 'ram_WB2Jw-1 : 0',`	`'redefine_param' => 1,`
`'instance_name' => 'single_port_ram0',`	`'global_param' => 'Localparam',`
`'type' => 'output',`	`'info' => 'Specify the multiplier implementation',`
`'intfc_port' => 'jwb_o'`	`'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',`
	`'type' => 'Combo-box',`
	`'default' => '"THREESTAGE"'`
	`},`
	`'cpu_OPTION_OPERAND_WIDTH' => {`
	`'info' => 'Parameter',`
	`'content' => '',`
	`'type' => 'Fixed',`
	`'default' => '32',`
	`'redefine_param' => 1,`
	`'global_param' => 'Localparam'`
	`},`
	`'cpu_OPTION_SHIFTER' => {`
	`'type' => 'Combo-box',`
	`'default' => '"BARREL"',`
	`'info' => 'Specify the shifter implementation',`
	`'content' => '"BARREL","SERIAL"',`
	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
	`},`
	`'cpu_FEATURE_DATACACHE' => {`
	`'content' => '"NONE","ENABLED"',`
	`'type' => 'Combo-box',`
	`'info' => '',`
	`'default' => '"ENABLED"',`
	`'redefine_param' => 1,`
	`'global_param' => 'Localparam'`
	`},`
	`'cpu_IRQ_NUM' => {`
	`'redefine_param' => 1,`
	`'global_param' => 'Localparam',`
	`'info' => undef,`
	`'content' => '',`
	`'default' => '32',`
	`'type' => 'Fixed'`
	`},`
	`'cpu_FEATURE_INSTRUCTIONCACHE' => {`
	`'redefine_param' => 1,`
	`'global_param' => 'Localparam',`
	`'info' => '',`
	`'default' => '"ENABLED"',`
	`'content' => '"NONE","ENABLED"',`
	`'type' => 'Combo-box'`
`}`	`}`
`}`	`}`
`},`	`},`
`'socket:ni[0]' => {`	`'ProNoC_jtag_uart0' => {`
	`'instance' => 'uart',`
	`'module' => 'ProNoC_jtag_uart',`
`'ports' => {`	`'ports' => {`
`'ni_current_e_addr' => {`	`'uart_RxD_wr_sim' => {`
`'range' => 'ni_EAw-1 : 0',`	`'range' => '',`
	`'intfc_port' => 'RxD_wr_sim',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'current_e_addr',`	`'intfc_name' => 'socket:RxD_sim[0]'`
`'instance_name' => 'ni_master0'`
`},`	`},`
`'ni_chan_in' => {`	`'uart_jtag_to_wb' => {`
`'range' => 'smartflit_chanel_t',`	`'range' => 'uart_J2WBw-1 : 0',`
`'intfc_port' => 'chan_in',`	`'intfc_port' => 'jwb_i',`
`'instance_name' => 'ni_master0',`	`'type' => 'input',`
`'type' => 'input'`	`'intfc_name' => 'socket:jtag_to_wb[0]'`
`},`	`},`
`'ni_chan_out' => {`	`'uart_wb_to_jtag' => {`
`'range' => 'smartflit_chanel_t',`	`'range' => 'uart_WB2Jw-1 : 0',`
`'instance_name' => 'ni_master0',`
`'type' => 'output',`	`'type' => 'output',`
`'intfc_port' => 'chan_out'`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'intfc_port' => 'jwb_o'`
`},`	`},`
`'ni_current_r_addr' => {`	`'uart_RxD_din_sim' => {`
`'range' => 'ni_RAw-1 : 0',`	`'range' => '7:0 ',`
`'intfc_port' => 'current_r_addr',`
`'type' => 'input',`	`'type' => 'input',`
`'instance_name' => 'ni_master0'`	`'intfc_name' => 'socket:RxD_sim[0]',`
`}`	`'intfc_port' => 'RxD_din_sim'`
`}`
`}`
`},`	`},`
`'parameters' => {`	`'uart_RxD_ready_sim' => {`
`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`	`'intfc_name' => 'socket:RxD_sim[0]',`
`'ram_JINDEXw' => '8',`	`'intfc_port' => 'RxD_ready_sim',`
`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`	`'type' => 'output',`
`'ram_JSTATUSw' => '8',`	`'range' => ''`
`'uart_JDw' => '32',`	`}`
`'uart_JINDEXw' => '8',`
`'ram_JTAG_CHAIN' => '4',`
`'ram_JDw' => 'ram_Dw',`
`'uart_JTAG_INDEX' => '126-CORE_ID',`
`'ram_JTAG_INDEX' => 'CORE_ID',`
`'ram_JAw' => '32',`
`'ram_Dw' => '32',`
`'uart_JAw' => '32',`
`'uart_JTAG_CHAIN' => '3',`
`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
`'uart_JSTATUSw' => '8',`
`'uart_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',`
`'ram_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',`
`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1'`
`},`	`},`
`'instance_ids' => {`	`'module_name' => 'pronoc_jtag_uart',`
`'timer0' => {`	`'category' => 'Communication',`
`'module' => 'timer',`
`'localparam' => {`	`'localparam' => {`
`'timer_CNTw' => {`	`'uart_BUFF_Aw' => {`
`'content' => '',`
`'info' => undef,`
`'default' => '32 ',`
`'type' => 'Fixed',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam'`
`},`
`'timer_SELw' => {`
`'info' => undef,`
`'content' => '',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'default' => '4',`	`'content' => '2,16,1',`
`'type' => 'Fixed'`	`'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',`
	`'type' => 'Spin-button',`
	`'default' => '4'`
`},`	`},`
`'timer_Aw' => {`	`'uart_Aw' => {`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '3',`	`'content' => '',`
`'info' => undef,`
`'content' => ''`
`},`
`'timer_PRESCALER_WIDTH' => {`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'default' => '8',`	`'default' => '1',`
`'type' => 'Spin-button',`	`'info' => 'Parameter'`
`'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.`


`',`
`'content' => '1,32,1'`
`},`	`},`
`'timer_Dw' => {`	`'uart_Dw' => {`
	`'content' => '',`
	`'info' => 'Parameter',`
`'default' => '32',`	`'default' => '32',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
	`'global_param' => 'Localparam'`
	`},`
	`'uart_SELw' => {`
	`'type' => 'Fixed',`
	`'default' => '4',`
	`'info' => 'Parameter',`
`'content' => '',`	`'content' => '',`
`'info' => undef`	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
`},`	`},`
`'timer_TAGw' => {`	`'uart_TAGw' => {`
	`'content' => '',`
	`'info' => 'Parameter',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '3',`	`'default' => '3',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'content' => '',`	`'global_param' => 'Localparam'`
`'info' => undef`
`}`	`}`
`},`	`},`
`'category' => 'Timer',`
`'instance' => 'timer',`
`'module_name' => 'timer'`
`},`
`'ProNoC_jtag_uart0' => {`
`'category' => 'Communication',`
`'parameters' => {`	`'parameters' => {`
`'uart_JTAG_CONNECT' => {`
`'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.`

`For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',`
`'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',`
`'redefine_param' => 1,`
`'global_param' => 'Parameter',`
`'default' => '"ALTERA_JTAG_WB"',`
`'type' => 'Combo-box'`
`},`
`'uart_JSTATUSw' => {`	`'uart_JSTATUSw' => {`
	`'type' => 'Fixed',`
	`'content' => '',`
`'global_param' => 'Parameter',`	`'global_param' => 'Parameter',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'default' => '8',`	`'default' => '8',`
`'type' => 'Fixed',`	`'info' => 'Parameter'`
`'info' => 'Parameter',`
`'content' => ''`
`},`	`},`
`'uart_J2WBw' => {`	`'uart_JINDEXw' => {`
`'info' => undef,`
`'content' => '',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter',`	`'global_param' => 'Parameter',`
`'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
`'type' => 'Fixed'`
`},`
`'uart_JDw' => {`
`'content' => '',`	`'content' => '',`
`'info' => 'Parameter',`	`'info' => 'Parameter',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '32',`	`'default' => '8'`
`'global_param' => 'Parameter',`
`'redefine_param' => 1`
`},`	`},`
`'uart_JINDEXw' => {`	`'uart_JTAG_CONNECT' => {`
`'content' => '',`	`'global_param' => 'Parameter',`
`'info' => 'Parameter',`
`'default' => '8',`
`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter'`	`'default' => '"ALTERA_JTAG_WB"',`
	`'type' => 'Combo-box',`
	`'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.`

	`For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',`
	`'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"'`
`},`	`},`
`'uart_JTAG_INDEX' => {`	`'uart_JTAG_INDEX' => {`
`'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',`
`'content' => '',`
`'global_param' => 'Parameter',`	`'global_param' => 'Parameter',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
	`'default' => '126-CORE_ID',`
	`'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',`
`'type' => 'Entry',`	`'type' => 'Entry',`
`'default' => '126-CORE_ID'`	`'content' => ''`
`},`	`},`
`'uart_JAw' => {`	`'uart_J2WBw' => {`
`'default' => '32',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'redefine_param' => 1,`
`'global_param' => 'Parameter',`
`'content' => '',`	`'content' => '',`
`'info' => 'Parameter'`	`'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
	`'info' => undef,`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1`
`},`	`},`
`'uart_JTAG_CHAIN' => {`	`'uart_JTAG_CHAIN' => {`
	`'content' => '1,2,3,4',`
`'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:`	`'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:`
`4: JTAG runtime memory programmers.`	`4: JTAG runtime memory programmers.`
`3: UART`	`3: UART`
`1,2: reserved',`	`1,2: reserved',`
`'content' => '1,2,3,4',`
`'global_param' => 'Parameter',`
`'redefine_param' => 0,`
`'default' => '3',`	`'default' => '3',`
`'type' => 'Combo-box'`	`'type' => 'Combo-box',`
	`'redefine_param' => 0,`
	`'global_param' => 'Parameter'`
`},`	`},`
`'uart_WB2Jw' => {`	`'uart_WB2Jw' => {`
`'redefine_param' => 1,`
`'global_param' => 'Parameter',`	`'global_param' => 'Parameter',`
	`'redefine_param' => 1,`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`	`'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`
`'info' => '',`	`'info' => '',`
`'content' => ''`	`'content' => ''`
`}`
`},`	`},`
`'module' => 'ProNoC_jtag_uart',`	`'uart_JAw' => {`
`'localparam' => {`	`'info' => 'Parameter',`
`'uart_BUFF_Aw' => {`	`'content' => '',`
`'default' => '4',`	`'type' => 'Fixed',`
`'type' => 'Spin-button',`	`'default' => '32',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Parameter'`
`'content' => '2,16,1',`
`'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.'`
`},`	`},`
`'uart_Dw' => {`	`'uart_JDw' => {`
`'global_param' => 'Localparam',`	`'content' => '',`
`'redefine_param' => 1,`	`'info' => 'Parameter',`
`'default' => '32',`	`'default' => '32',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'info' => 'Parameter',`	`'redefine_param' => 1,`
`'content' => ''`	`'global_param' => 'Parameter'`
	`}`
	`}`
`},`	`},`
`'uart_TAGw' => {`	`'single_port_ram0' => {`
	`'localparam' => {`
	`'ram_BYTE_WR_EN' => {`
	`'default' => '"YES"',`
	`'type' => 'Combo-box',`
	`'info' => 'Byte enable',`
	`'content' => '"YES","NO"',`
	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
	`},`
	`'ram_TAGw' => {`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '3',`	`'default' => '3',`
`'info' => 'Parameter',`
`'content' => ''`
`},`
`'uart_SELw' => {`
`'content' => '',`	`'content' => '',`
`'info' => 'Parameter',`	`'info' => 'Parameter'`
`'type' => 'Fixed',`
`'default' => '4',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam'`
`},`	`},`
`'uart_Aw' => {`	`'ram_INIT_FILE_PATH' => {`
`'info' => 'Parameter',`
`'content' => '',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'default' => '1',`	`'global_param' => 'Localparam',`
	`'info' => undef,`
	`'content' => '',`
	`'default' => 'SW_LOC',`
`'type' => 'Fixed'`	`'type' => 'Fixed'`
`}`
`},`
`'instance' => 'uart',`
`'module_name' => 'pronoc_jtag_uart',`
`'ports' => {`
`'uart_RxD_wr_sim' => {`
`'intfc_port' => 'RxD_wr_sim',`
`'type' => 'input',`
`'intfc_name' => 'socket:RxD_sim[0]',`
`'range' => ''`
`},`
`'uart_wb_to_jtag' => {`
`'intfc_port' => 'jwb_o',`
`'type' => 'output',`
`'range' => 'uart_WB2Jw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]'`
`},`
`'uart_RxD_din_sim' => {`
`'intfc_name' => 'socket:RxD_sim[0]',`
`'range' => '7:0 ',`
`'intfc_port' => 'RxD_din_sim',`
`'type' => 'input'`
`},`
`'uart_jtag_to_wb' => {`
`'type' => 'input',`
`'intfc_port' => 'jwb_i',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'uart_J2WBw-1 : 0'`
`},`
`'uart_RxD_ready_sim' => {`
`'type' => 'output',`
`'intfc_port' => 'RxD_ready_sim',`
`'intfc_name' => 'socket:RxD_sim[0]',`
`'range' => ''`
`}`
`}`
`},`	`},`
`'wishbone_bus0' => {`	`'ram_BURST_MODE' => {`
`'localparam' => {`
`'bus_SELw' => {`
`'type' => 'Fixed',`
`'default' => 'bus_Dw/8',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'content' => '',`	`'default' => '"ENABLED"',`
`'info' => undef`	`'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',`
	`'type' => 'Combo-box',`
	`'content' => '"DISABLED","ENABLED"'`
`},`	`},`
`'bus_CTIw' => {`	`'ram_INITIAL_EN' => {`
`'type' => 'Fixed',`	`'redefine_param' => 1,`
`'default' => '3',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
	`'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',`
	`'default' => '"YES"',`
	`'content' => '"YES","NO"',`
	`'type' => 'Combo-box'`
	`},`
	`'ram_CTIw' => {`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
	`'global_param' => 'Localparam',`
`'content' => '',`	`'content' => '',`
`'info' => undef`	`'info' => 'Parameter',`
	`'type' => 'Fixed',`
	`'default' => '3'`
`},`	`},`
`'bus_S' => {`	`'ram_CORE_NUM' => {`
`'content' => '1,256,1',`	`'content' => '',`
`'info' => 'Number of wishbone slave interface',`	`'info' => 'Parameter',`
`'default' => '4',`	`'default' => 'CORE_ID',`
`'type' => 'Spin-button',`	`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam'`	`'global_param' => 'Localparam'`
`},`	`},`
`'bus_TAGw' => {`	`'ram_WB_Aw' => {`
`'content' => '',`	`'redefine_param' => 1,`
`'info' => undef,`
`'type' => 'Fixed',`
`'default' => '3',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1`	`'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',`
`},`	`'content' => '4,31,1',`
`'bus_M' => {`
`'content' => '1,256,1',`
`'info' => 'Number of wishbone master interface',`
`'type' => 'Spin-button',`	`'type' => 'Spin-button',`
`'default' => ' 4',`	`'default' => '20'`
`'global_param' => 'Localparam',`
`'redefine_param' => 1`
`},`	`},`
`'bus_Dw' => {`	`'ram_SELw' => {`
`'info' => 'The wishbone Bus data width in bits.',`
`'content' => '8,512,8',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'type' => 'Spin-button',`	`'default' => 'ram_Dw/8',`
`'default' => '32'`	`'info' => 'Parameter',`
	`'type' => 'Fixed',`
	`'content' => ''`
`},`	`},`
`'bus_Aw' => {`	`'ram_Aw' => {`
`'info' => 'The wishbone Bus address width',`
`'content' => '4,128,1',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'default' => '32',`	`'info' => 'Memory address width',`
	`'content' => '4,31,1',`
	`'default' => '14',`
`'type' => 'Spin-button'`	`'type' => 'Spin-button'`
`},`	`},`
`'bus_BTEw' => {`	`'ram_FPGA_VENDOR' => {`
`'info' => undef,`	`'global_param' => 'Localparam',`
	`'redefine_param' => 1,`
	`'type' => 'Combo-box',`
	`'default' => '"ALTERA"',`
	`'content' => '"ALTERA","XILINX","GENERIC"',`
	`'info' => ''`
	`},`
	`'ram_BTEw' => {`
	`'info' => 'Parameter',`
`'content' => '',`	`'content' => '',`
	`'default' => '2',`
	`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
	`'global_param' => 'Localparam'`
	`},`
	`'ram_MEM_CONTENT_FILE_NAME' => {`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'default' => '2 ',`	`'redefine_param' => 1,`
`'type' => 'Fixed'`	`'default' => '"ram0"',`
	`'info' => 'MEM_FILE_NAME:`
	`The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.`

	`File Path:`
	`For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.`
	`For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}`

	`file_type:`
	`bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.`
	`memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.`
	`mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',`
	`'type' => 'Entry',`
	`'content' => ''`
`}`	`}`
`},`	`},`
`'module' => 'wishbone_bus',`	`'parameters' => {`
`'category' => 'Bus',`	`'ram_JSTATUSw' => {`
`'module_name' => 'wishbone_bus',`	`'type' => 'Fixed',`
`'instance' => 'bus'`	`'default' => '8',`
	`'info' => 'Parameter',`
	`'content' => '',`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1`
`},`	`},`
`'clk_source0' => {`	`'ram_JAw' => {`
`'category' => 'Source',`	`'redefine_param' => 1,`
`'module' => 'clk_source',`	`'global_param' => 'Parameter',`
`'localparam' => {`	`'info' => 'Parameter',`
`'source_FPGA_VENDOR' => {`	`'default' => '32',`
`'default' => '"ALTERA"',`	`'content' => '',`
	`'type' => 'Fixed'`
	`},`
	`'ram_JTAG_CONNECT' => {`
	`'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',`
`'type' => 'Combo-box',`	`'type' => 'Combo-box',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'content' => '"ALTERA","XILINX"',`	`'global_param' => 'Parameter',`
`'info' => ''`	`'info' => 'JTAG_CONNECT:`
`}`	`if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',`
	`'default' => '"ALTERA_JTAG_WB"'`
`},`	`},`
`'ports' => {`	`'ram_Dw' => {`
`'source_clk_in' => {`	`'global_param' => 'Parameter',`
`'intfc_name' => 'plug:clk[0]',`	`'redefine_param' => 1,`
`'range' => '',`	`'default' => '32',`
`'type' => 'input',`	`'type' => 'Spin-button',`
`'intfc_port' => 'clk_i'`	`'info' => 'Memory data width in Bits.',`
	`'content' => '8,1024,1'`
`},`	`},`
`'source_reset_in' => {`	`'ram_WB2Jw' => {`
`'intfc_port' => 'reset_i',`	`'global_param' => 'Parameter',`
`'type' => 'input',`	`'redefine_param' => 1,`
`'intfc_name' => 'plug:reset[0]',`	`'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
`'range' => ''`	`'info' => undef,`
`}`	`'type' => 'Fixed',`
	`'content' => ''`
`},`	`},`
`'instance' => 'source',`	`'ram_J2WBw' => {`
`'module_name' => 'clk_source'`	`'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
	`'info' => undef,`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1,`
	`'type' => 'Fixed',`
	`'content' => ''`
`},`	`},`
`'ni_master0' => {`	`'ram_JTAG_CHAIN' => {`
`'ports' => {`	`'content' => '1,2,3,4',`
`'ni_current_r_addr' => {`	`'type' => 'Combo-box',`
`'type' => 'input',`	`'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:`
`'intfc_port' => 'current_r_addr',`	`4: JTAG runtime memory programmers.`
`'intfc_name' => 'socket:ni[0]',`	`3: UART`
`'range' => 'ni_RAw-1 : 0'`	`1,2: reserved',`
`},`	`'default' => '4',`
`'ni_chan_out' => {`	`'redefine_param' => 0,`
`'type' => 'output',`	`'global_param' => 'Parameter'`
`'intfc_port' => 'chan_out',`
`'range' => 'smartflit_chanel_t',`
`'intfc_name' => 'socket:ni[0]'`
`},`
`'ni_chan_in' => {`
`'intfc_port' => 'chan_in',`
`'type' => 'input',`
`'intfc_name' => 'socket:ni[0]',`
`'range' => 'smartflit_chanel_t'`
`},`
`'ni_current_e_addr' => {`
`'range' => 'ni_EAw-1 : 0',`
`'intfc_name' => 'socket:ni[0]',`
`'intfc_port' => 'current_e_addr',`
`'type' => 'input'`
`}`
`},`	`},`
`'instance' => 'ni',`	`'ram_JDw' => {`
`'module_name' => 'ni_master',`	`'info' => 'Parameter',`
`'category' => 'NoC',`
`'parameters' => {`
`'ni_RAw' => {`
`'content' => '',`	`'content' => '',`
`'info' => undef,`	`'default' => 'ram_Dw',`
`'default' => '16',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'redefine_param' => 0,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter'`	`'global_param' => 'Parameter'`
`},`	`},`
`'ni_EAw' => {`	`'ram_JINDEXw' => {`
`'global_param' => 'Parameter',`	`'default' => '8',`
`'redefine_param' => 0,`
`'default' => '16',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'info' => undef,`	`'content' => '',`
`'content' => ''`	`'info' => 'Parameter',`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1`
	`},`
	`'ram_JTAG_INDEX' => {`
	`'default' => 'CORE_ID',`
	`'type' => 'Entry',`
	`'content' => '',`
	`'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.`

	`In case you have \'n\' memory in each processing core you can define their index as "nCORE_ID+1 , nCORE_ID+2 ...n*CORE_ID+n-1).`

	`You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).`

	`',`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1`
`}`	`}`
`},`	`},`
`'module' => 'ni_master',`	`'ports' => {`
`'localparam' => {`	`'ram_wb_to_jtag' => {`
`'ni_MAX_BURST_SIZE' => {`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'info' => 'Maximum burst size in words.`	`'intfc_port' => 'jwb_o',`
`The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',`	`'type' => 'output',`
`'content' => '2,4,8,16,32,64,128,256,512,1024,2048',`	`'range' => 'ram_WB2Jw-1 : 0'`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'default' => '16',`
`'type' => 'Combo-box'`
`},`	`},`
`'ni_MAX_TRANSACTION_WIDTH' => {`	`'ram_jtag_to_wb' => {`
`'default' => '13',`	`'range' => 'ram_J2WBw-1 : 0',`
`'type' => 'Spin-button',`	`'intfc_port' => 'jwb_i',`
`'global_param' => 'Localparam',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'redefine_param' => 1,`	`'type' => 'input'`
`'content' => '4,32,1',`	`}`
`'info' => 'maximum packet size width in words.`
`The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.'`
`},`	`},`
`'ni_M_Aw' => {`	`'module' => 'single_port_ram',`
`'redefine_param' => 1,`	`'instance' => 'ram',`
`'global_param' => 'Localparam',`	`'module_name' => 'wb_single_port_ram',`
`'type' => 'Fixed',`	`'category' => 'RAM'`
`'default' => '32',`
`'info' => 'Parameter',`
`'content' => 'Dw'`
`},`	`},`
`'ni_S_Aw' => {`	`'clk_source0' => {`
`'info' => 'Parameter',`	`'ports' => {`
`'content' => '',`	`'source_clk_in' => {`
`'redefine_param' => 1,`	`'range' => '',`
`'global_param' => 'Localparam',`	`'intfc_port' => 'clk_i',`
`'default' => '8',`	`'type' => 'input',`
`'type' => 'Fixed'`	`'intfc_name' => 'plug:clk[0]'`
`},`	`},`
`'ni_SELw' => {`	`'source_reset_in' => {`
`'info' => 'Parameter',`	`'range' => '',`
`'content' => '',`	`'intfc_port' => 'reset_i',`
	`'intfc_name' => 'plug:reset[0]',`
	`'type' => 'input'`
	`}`
	`},`
	`'localparam' => {`
	`'source_FPGA_VENDOR' => {`
	`'content' => '"ALTERA","XILINX"',`
	`'info' => '',`
	`'default' => '"ALTERA"',`
	`'type' => 'Combo-box',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam'`
`'type' => 'Fixed',`	`}`
`'default' => '4'`	`},`
	`'module' => 'clk_source',`
	`'instance' => 'source',`
	`'module_name' => 'clk_source',`
	`'category' => 'Source'`
`},`	`},`
	`'ni_master0' => {`
	`'localparam' => {`
`'ni_TAGw' => {`	`'ni_TAGw' => {`
`'default' => '3',`	`'default' => '3',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'info' => 'Parameter',`
`'global_param' => 'Localparam',`
`'content' => '',`	`'content' => '',`
`'info' => 'Parameter'`	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
`},`	`},`
`'ni_CRC_EN' => {`	`'ni_CRC_EN' => {`
	`'default' => '"NO"',`
	`'type' => 'Combo-box',`
	`'content' => '"YES","NO"',`
`'info' => 'The parameter can be selected as "YES" or "NO".`	`'info' => 'The parameter can be selected as "YES" or "NO".`
`If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',`	`If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',`
`'content' => '"YES","NO"',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1`
`'type' => 'Combo-box',`
`'default' => '"NO"'`
`},`	`},`
`'ni_Dw' => {`	`'ni_SELw' => {`
`'default' => '32',`
`'type' => 'Spin-button',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'content' => '32,256,8',`
`'info' => 'wishbone_bus data width in bits.'`
`},`
`'ni_HDATA_PRECAPw' => {`
`'type' => 'Spin-button',`
`'default' => '0',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'content' => '',`
`'content' => '0,8,1',`	`'info' => 'Parameter',`
`'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.'`	`'default' => '4',`
`}`	`'type' => 'Fixed'`
`}`
`},`	`},`
`'mor1kx0' => {`	`'ni_MAX_BURST_SIZE' => {`
`'category' => 'Processor',`
`'localparam' => {`
`'cpu_FEATURE_INSTRUCTIONCACHE' => {`
`'info' => '',`
`'content' => '"NONE","ENABLED"',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'type' => 'Combo-box',`	`'info' => 'Maximum burst size in words.`
`'default' => '"ENABLED"'`	`The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',`
	`'default' => '16',`
	`'content' => '2,4,8,16,32,64,128,256,512,1024,2048',`
	`'type' => 'Combo-box'`
`},`	`},`
`'cpu_OPTION_SHIFTER' => {`	`'ni_MAX_TRANSACTION_WIDTH' => {`
`'info' => 'Specify the shifter implementation',`
`'content' => '"BARREL","SERIAL"',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'type' => 'Combo-box',`	`'info' => 'maximum packet size width in words.`
`'default' => '"BARREL"'`	`The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',`
	`'content' => '4,32,1',`
	`'type' => 'Spin-button',`
	`'default' => '13'`
`},`	`},`
`'cpu_FEATURE_DMMU' => {`	`'ni_M_Aw' => {`
`'info' => '',`
`'content' => '"NONE","ENABLED"',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'default' => '"ENABLED"',`
`'type' => 'Combo-box'`
`},`
`'cpu_FEATURE_MULTIPLIER' => {`
`'type' => 'Combo-box',`
`'default' => '"THREESTAGE"',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'type' => 'Fixed',`
`'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',`	`'default' => '32',`
`'info' => 'Specify the multiplier implementation'`	`'content' => 'Dw',`
	`'info' => 'Parameter'`
`},`	`},`
`'cpu_OPTION_DCACHE_SNOOP' => {`	`'ni_Dw' => {`
`'default' => '"ENABLED"',`
`'type' => 'Combo-box',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'content' => '"NONE","ENABLED"',`	`'redefine_param' => 1,`
`'info' => ''`	`'default' => '32',`
	`'info' => 'wishbone_bus data width in bits.',`
	`'type' => 'Spin-button',`
	`'content' => '32,256,8'`
`},`	`},`
`'cpu_OPTION_OPERAND_WIDTH' => {`	`'ni_S_Aw' => {`
	`'default' => '8',`
	`'type' => 'Fixed',`
`'info' => 'Parameter',`	`'info' => 'Parameter',`
`'content' => '',`	`'content' => '',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'type' => 'Fixed',`	`'redefine_param' => 1`
`'default' => '32'`
`},`	`},`
`'cpu_FEATURE_IMMU' => {`	`'ni_HDATA_PRECAPw' => {`
`'info' => '',`	`'default' => '0',`
`'content' => '"NONE","ENABLED"',`	`'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'type' => 'Combo-box',`	`'type' => 'Spin-button',`
`'default' => '"ENABLED"'`	`'content' => '0,8,1'`
`},`	`}`
`'cpu_FEATURE_DIVIDER' => {`
`'default' => '"SERIAL"',`
`'type' => 'Combo-box',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`
`'content' => '"SERIAL","NONE"',`
`'info' => 'Specify the divider implementation'`
`},`	`},`
`'cpu_IRQ_NUM' => {`	`'parameters' => {`
	`'ni_EAw' => {`
	`'redefine_param' => 0,`
	`'global_param' => 'Parameter',`
`'info' => undef,`	`'info' => undef,`
`'content' => '',`	`'content' => '',`
`'global_param' => 'Localparam',`	`'default' => '16',`
`'redefine_param' => 1,`	`'type' => 'Fixed'`
	`},`
	`'ni_RAw' => {`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '32'`	`'default' => '16',`
	`'content' => '',`
	`'info' => undef,`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 0`
	`}`
`},`	`},`
`'cpu_FEATURE_DATACACHE' => {`	`'module' => 'ni_master',`
`'info' => '',`	`'instance' => 'ni',`
`'content' => '"NONE","ENABLED"',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'default' => '"ENABLED"',`
`'type' => 'Combo-box'`
`}`
`},`
`'module' => 'mor1kx',`
`'module_name' => 'mor1k',`
`'ports' => {`	`'ports' => {`
`'cpu_cpu_en' => {`	`'ni_chan_in' => {`
`'intfc_name' => 'plug:enable[0]',`
`'range' => '',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'enable_i'`	`'intfc_port' => 'chan_in',`
`}`	`'intfc_name' => 'socket:ni[0]',`
	`'range' => 'smartflit_chanel_t'`
`},`	`},`
`'instance' => 'cpu'`	`'ni_current_r_addr' => {`
	`'intfc_port' => 'current_r_addr',`
	`'type' => 'input',`
	`'intfc_name' => 'socket:ni[0]',`
	`'range' => 'ni_RAw-1 : 0'`
`},`	`},`
`'single_port_ram0' => {`	`'ni_current_e_addr' => {`
`'instance' => 'ram',`	`'intfc_name' => 'socket:ni[0]',`
`'module_name' => 'wb_single_port_ram',`
`'ports' => {`
`'ram_jtag_to_wb' => {`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'current_e_addr',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'range' => 'ni_EAw-1 : 0'`
`'range' => 'ram_J2WBw-1 : 0'`
`},`	`},`
`'ram_wb_to_jtag' => {`	`'ni_chan_out' => {`
	`'range' => 'smartflit_chanel_t',`
`'type' => 'output',`	`'type' => 'output',`
`'intfc_port' => 'jwb_o',`	`'intfc_name' => 'socket:ni[0]',`
`'range' => 'ram_WB2Jw-1 : 0',`	`'intfc_port' => 'chan_out'`
`'intfc_name' => 'socket:jtag_to_wb[0]'`
`}`	`}`
`},`	`},`
`'category' => 'RAM',`	`'module_name' => 'ni_master',`
`'module' => 'single_port_ram',`	`'category' => 'NoC'`
`'parameters' => {`
`'ram_JSTATUSw' => {`
`'content' => '',`
`'info' => 'Parameter',`
`'default' => '8',`
`'type' => 'Fixed',`
`'global_param' => 'Parameter',`
`'redefine_param' => 1`
`},`	`},`
`'ram_JINDEXw' => {`	`'timer0' => {`
`'default' => '8',`	`'category' => 'Timer',`
	`'module_name' => 'timer',`
	`'module' => 'timer',`
	`'instance' => 'timer',`
	`'localparam' => {`
	`'timer_Aw' => {`
	`'default' => '3',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'redefine_param' => 1,`
`'global_param' => 'Parameter',`
`'content' => '',`	`'content' => '',`
`'info' => 'Parameter'`
`},`
`'ram_J2WBw' => {`
`'redefine_param' => 1,`
`'global_param' => 'Parameter',`
`'type' => 'Fixed',`
`'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
`'info' => undef,`	`'info' => undef,`
`'content' => ''`	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
`},`	`},`
`'ram_WB2Jw' => {`	`'timer_Dw' => {`
`'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`	`'default' => '32',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'info' => undef,`
`'global_param' => 'Parameter',`
`'content' => '',`	`'content' => '',`
`'info' => undef`	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
`},`	`},`
`'ram_Dw' => {`	`'timer_CNTw' => {`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter',`	`'global_param' => 'Localparam',`
`'type' => 'Spin-button',`	`'content' => '',`
	`'info' => undef,`
`'default' => '32',`	`'default' => '32',`
`'info' => 'Memory data width in Bits.',`	`'type' => 'Fixed'`
`'content' => '8,1024,1'`
`},`	`},`
`'ram_JTAG_INDEX' => {`	`'timer_SELw' => {`
`'global_param' => 'Parameter',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'default' => 'CORE_ID',`	`'global_param' => 'Localparam',`
`'type' => 'Entry',`	`'info' => undef,`
`'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.`

`In case you have \'n\' memory in each processing core you can define their index as "nCORE_ID+1 , nCORE_ID+2 ...n*CORE_ID+n-1).`

`You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).`

`',`
`'content' => ''`
`},`
`'ram_JAw' => {`
`'info' => 'Parameter',`
`'content' => '',`	`'content' => '',`
`'global_param' => 'Parameter',`	`'default' => '4',`
`'redefine_param' => 1,`
`'default' => '32',`
`'type' => 'Fixed'`	`'type' => 'Fixed'`
`},`	`},`
`'ram_JTAG_CONNECT' => {`	`'timer_PRESCALER_WIDTH' => {`
`'type' => 'Combo-box',`
`'default' => '"ALTERA_JTAG_WB"',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter',`	`'global_param' => 'Localparam',`
`'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',`	`'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.`
`'info' => 'JTAG_CONNECT:`
`if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '`
	`',`
	`'default' => '8',`
	`'content' => '1,32,1',`
	`'type' => 'Spin-button'`
`},`	`},`
`'ram_JDw' => {`	`'timer_TAGw' => {`
`'global_param' => 'Parameter',`
`'redefine_param' => 1,`
`'default' => 'ram_Dw',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'info' => 'Parameter',`	`'default' => '3',`
`'content' => ''`	`'info' => undef,`
`},`	`'content' => '',`
`'ram_JTAG_CHAIN' => {`	`'global_param' => 'Localparam',`
`'content' => '1,2,3,4',`	`'redefine_param' => 1`
`'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:`	`}`
`4: JTAG runtime memory programmers.`
`3: UART`
`1,2: reserved',`
`'default' => '4',`
`'type' => 'Combo-box',`
`'global_param' => 'Parameter',`
`'redefine_param' => 0`
`}`	`}`
`},`	`},`
	`'wishbone_bus0' => {`
`'localparam' => {`	`'localparam' => {`
`'ram_CTIw' => {`	`'bus_S' => {`
`'content' => '',`	`'content' => '1,256,1',`
`'info' => 'Parameter',`	`'type' => 'Spin-button',`
`'default' => '3',`
`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam'`	`'global_param' => 'Localparam',`
	`'info' => 'Number of wishbone slave interface',`
	`'default' => '4'`
`},`	`},`
`'ram_TAGw' => {`	`'bus_SELw' => {`
`'default' => '3',`
`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
	`'info' => undef,`
	`'default' => 'bus_Dw/8',`
`'content' => '',`	`'content' => '',`
`'info' => 'Parameter'`	`'type' => 'Fixed'`
`},`	`},`
`'ram_SELw' => {`	`'bus_Aw' => {`
`'default' => 'ram_Dw/8',`	`'type' => 'Spin-button',`
`'type' => 'Fixed',`	`'default' => '32',`
	`'info' => 'The wishbone Bus address width',`
	`'content' => '4,128,1',`
	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
	`},`
	`'bus_TAGw' => {`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
	`'info' => undef,`
	`'default' => '3',`
`'content' => '',`	`'content' => '',`
`'info' => 'Parameter'`	`'type' => 'Fixed'`
`},`	`},`
`'ram_FPGA_VENDOR' => {`	`'bus_M' => {`
`'type' => 'Combo-box',`
`'default' => '"ALTERA"',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'content' => '"ALTERA","XILINX","GENERIC"',`	`'type' => 'Spin-button',`
`'info' => ''`	`'default' => ' 4',`
	`'info' => 'Number of wishbone master interface',`
	`'content' => '1,256,1'`
`},`	`},`
`'ram_BYTE_WR_EN' => {`	`'bus_BTEw' => {`
	`'default' => '2 ',`
	`'info' => undef,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'default' => '"YES"',`
`'type' => 'Combo-box',`
`'info' => 'Byte enable',`
`'content' => '"YES","NO"'`
`},`
`'ram_CORE_NUM' => {`
`'default' => 'CORE_ID',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'content' => ''`
`'global_param' => 'Localparam',`
`'content' => '',`
`'info' => 'Parameter'`
`},`	`},`
`'ram_INIT_FILE_PATH' => {`	`'bus_CTIw' => {`
`'content' => '',`	`'content' => '',`
`'info' => undef,`	`'info' => undef,`
`'default' => 'SW_LOC',`	`'default' => '3',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam'`	`'global_param' => 'Localparam'`
`},`	`},`
`'ram_INITIAL_EN' => {`	`'bus_Dw' => {`
`'default' => '"YES"',`
`'type' => 'Combo-box',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'content' => '"YES","NO"',`
`'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'`
`},`
`'ram_WB_Aw' => {`
`'content' => '4,31,1',`
`'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',`
`'default' => '20',`
`'type' => 'Spin-button',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1`	`'content' => '8,512,8',`
	`'info' => 'The wishbone Bus data width in bits.',`
	`'default' => '32',`
	`'type' => 'Spin-button'`
	`}`
`},`	`},`
`'ram_Aw' => {`	`'instance' => 'bus',`
`'content' => '4,31,1',`	`'module' => 'wishbone_bus',`
`'info' => 'Memory address width',`	`'module_name' => 'wishbone_bus',`
`'type' => 'Spin-button',`	`'category' => 'Bus'`
`'default' => '14',`	`}`
`'redefine_param' => 1,`
`'global_param' => 'Localparam'`
`},`	`},`
`'ram_MEM_CONTENT_FILE_NAME' => {`	`'interface' => {`
`'content' => '',`	`'plug:reset[0]' => {`
`'info' => 'MEM_FILE_NAME:`	`'ports' => {`
`The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.`	`'source_reset_in' => {`
	`'instance_name' => 'clk_source0',`
`File Path:`	`'range' => '',`
`For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.`	`'intfc_port' => 'reset_i',`
`For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}`	`'type' => 'input'`

`file_type:`
`bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.`
`memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.`
`mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',`
`'type' => 'Entry',`
`'default' => '"ram0"',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam'`
`},`
`'ram_BTEw' => {`
`'default' => '2',`
`'type' => 'Fixed',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'content' => '',`
`'info' => 'Parameter'`
`},`
`'ram_BURST_MODE' => {`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'default' => '"ENABLED"',`
`'type' => 'Combo-box',`
`'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',`
`'content' => '"DISABLED","ENABLED"'`
`}`
`}`	`}`
`}`	`}`
`},`	`},`
`'tiles' => {`	`'socket:RxD_sim[0]' => {`
`'0' => {`	`'ports' => {`
`'parameters' => {`	`'uart_RxD_din_sim' => {`
`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`	`'intfc_port' => 'RxD_din_sim',`
`'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`	`'type' => 'input',`
`'uart_JSTATUSw' => '8',`	`'range' => '7:0 ',`
`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`	`'instance_name' => 'ProNoC_jtag_uart0'`
`'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
`'ram_JINDEXw' => '8',`
`'ram_JSTATUSw' => '8',`
`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
`'uart_JDw' => '32',`
`'ram_Aw' => '14',`
`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
`'uart_JTAG_CHAIN' => '3',`
`'uart_JINDEXw' => '8',`
`'ram_JTAG_CHAIN' => '4',`
`'ram_JDw' => 'ram_Dw',`
`'uart_JTAG_INDEX' => '126-CORE_ID',`
`'ram_JTAG_INDEX' => 'CORE_ID',`
`'ram_JAw' => '32',`
`'uart_JAw' => '32',`
`'ram_Dw' => '32'`
`}`
`},`	`},`
`'1' => {`	`'uart_RxD_ready_sim' => {`
`'parameters' => {`	`'range' => '',`
`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`	`'instance_name' => 'ProNoC_jtag_uart0',`
`'ram_Aw' => '14',`	`'intfc_port' => 'RxD_ready_sim',`
`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`	`'type' => 'output'`
`'ram_JSTATUSw' => '8',`
`'uart_JDw' => '32',`
`'ram_JINDEXw' => '8',`
`'uart_JTAG_INDEX' => '126-CORE_ID',`
`'ram_JAw' => '32',`
`'ram_Dw' => '32',`
`'uart_JAw' => '32',`
`'ram_JTAG_INDEX' => 'CORE_ID',`
`'uart_JINDEXw' => '8',`
`'ram_JTAG_CHAIN' => '4',`
`'ram_JDw' => 'ram_Dw',`
`'uart_JTAG_CHAIN' => '3',`
`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
`'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
`'uart_JSTATUSw' => '8',`
`'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1'`
`}`
`},`	`},`
`'2' => {`	`'uart_RxD_wr_sim' => {`
`'parameters' => {`	`'range' => '',`
`'uart_JINDEXw' => '8',`	`'instance_name' => 'ProNoC_jtag_uart0',`
`'ram_JTAG_CHAIN' => '4',`	`'intfc_port' => 'RxD_wr_sim',`
`'ram_JDw' => 'ram_Dw',`	`'type' => 'input'`
`'uart_JTAG_INDEX' => '126-CORE_ID',`	`}`
`'ram_JAw' => '32',`
`'ram_JTAG_INDEX' => 'CORE_ID',`
`'ram_Dw' => '32',`
`'uart_JAw' => '32',`
`'uart_JTAG_CHAIN' => '3',`
`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
`'ram_JINDEXw' => '8',`
`'ram_JSTATUSw' => '8',`
`'uart_JDw' => '32',`
`'ram_Aw' => '14',`
`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
`'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`
`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
`'uart_JSTATUSw' => '8',`
`'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"'`
`}`	`}`
`},`	`},`
`'3' => {`	`'plug:enable[0]' => {`
`'parameters' => {`	`'ports' => {`
`'ram_Dw' => '32',`	`'cpu_cpu_en' => {`
`'ram_JAw' => '32',`	`'instance_name' => 'mor1kx0',`
`'ram_JTAG_INDEX' => 'CORE_ID',`	`'range' => '',`
`'uart_JAw' => '32',`	`'intfc_port' => 'enable_i',`
`'uart_JTAG_INDEX' => '126-CORE_ID',`	`'type' => 'input'`
`'ram_JDw' => 'ram_Dw',`
`'uart_JINDEXw' => '8',`
`'ram_JTAG_CHAIN' => '4',`
`'uart_JTAG_CHAIN' => '3',`
`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
`'ram_Aw' => '14',`
`'ram_JSTATUSw' => '8',`
`'uart_JDw' => '32',`
`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
`'ram_JINDEXw' => '8',`
`'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`
`'uart_JSTATUSw' => '8',`
`'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1'`
`}`	`}`
`}`	`}`
`},`	`},`
	`'plug:clk[0]' => {`
`'ports' => {`	`'ports' => {`
`'uart_RxD_din_sim' => {`
`'intfc_name' => 'socket:RxD_sim[0]',`
`'range' => '7:0 ',`
`'intfc_port' => 'RxD_din_sim',`
`'type' => 'input',`
`'instance_name' => 'ProNoC_jtag_uart0'`
`},`
`'ram_wb_to_jtag' => {`
`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'ram_WB2Jw-1 : 0',`
`'instance_name' => 'single_port_ram0',`
`'type' => 'output',`
`'intfc_port' => 'jwb_o'`
`},`
`'source_clk_in' => {`	`'source_clk_in' => {`
`'intfc_name' => 'plug:clk[0]',`	`'intfc_port' => 'clk_i',`
`'range' => '',`
`'instance_name' => 'clk_source0',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'clk_i'`
`},`
`'source_reset_in' => {`
`'intfc_name' => 'plug:reset[0]',`
`'range' => '',`	`'range' => '',`
`'instance_name' => 'clk_source0',`	`'instance_name' => 'clk_source0'`
	`}`
	`}`
	`},`
	`'socket:jtag_to_wb[0]' => {`
	`'ports' => {`
	`'ram_jtag_to_wb' => {`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'reset_i'`	`'intfc_port' => 'jwb_i',`
	`'range' => 'ram_J2WBw-1 : 0',`
	`'instance_name' => 'single_port_ram0'`
`},`	`},`
`'uart_RxD_ready_sim' => {`	`'uart_wb_to_jtag' => {`
`'intfc_port' => 'RxD_ready_sim',`
`'type' => 'output',`	`'type' => 'output',`
`'instance_name' => 'ProNoC_jtag_uart0',`	`'intfc_port' => 'jwb_o',`
`'intfc_name' => 'socket:RxD_sim[0]',`	`'range' => 'uart_WB2Jw-1 : 0',`
`'range' => ''`	`'instance_name' => 'ProNoC_jtag_uart0'`
`},`	`},`
`'uart_jtag_to_wb' => {`	`'uart_jtag_to_wb' => {`
`'type' => 'input',`
`'intfc_port' => 'jwb_i',`
`'instance_name' => 'ProNoC_jtag_uart0',`
`'range' => 'uart_J2WBw-1 : 0',`	`'range' => 'uart_J2WBw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]'`
`},`
`'ni_current_r_addr' => {`
`'intfc_name' => 'socket:ni[0]',`
`'range' => 'ni_RAw-1 : 0',`
`'instance_name' => 'ni_master0',`
`'type' => 'input',`
`'intfc_port' => 'current_r_addr'`
`},`
`'uart_RxD_wr_sim' => {`
`'range' => '',`
`'intfc_name' => 'socket:RxD_sim[0]',`
`'instance_name' => 'ProNoC_jtag_uart0',`	`'instance_name' => 'ProNoC_jtag_uart0',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'RxD_wr_sim'`	`'intfc_port' => 'jwb_i'`
	`},`
	`'ram_wb_to_jtag' => {`
	`'range' => 'ram_WB2Jw-1 : 0',`
	`'instance_name' => 'single_port_ram0',`
	`'intfc_port' => 'jwb_o',`
	`'type' => 'output'`
	`}`
	`}`
`},`	`},`
	`'socket:ni[0]' => {`
	`'ports' => {`
`'ni_chan_out' => {`	`'ni_chan_out' => {`
`'instance_name' => 'ni_master0',`	`'instance_name' => 'ni_master0',`
`'type' => 'output',`
`'intfc_port' => 'chan_out',`
`'range' => 'smartflit_chanel_t',`	`'range' => 'smartflit_chanel_t',`
`'intfc_name' => 'socket:ni[0]'`	`'type' => 'output',`
	`'intfc_port' => 'chan_out'`
`},`	`},`
`'ni_chan_in' => {`	`'ni_chan_in' => {`
`'intfc_name' => 'socket:ni[0]',`
`'range' => 'smartflit_chanel_t',`
`'type' => 'input',`
`'intfc_port' => 'chan_in',`	`'intfc_port' => 'chan_in',`
	`'type' => 'input',`
	`'range' => 'smartflit_chanel_t',`
`'instance_name' => 'ni_master0'`	`'instance_name' => 'ni_master0'`
`},`	`},`
`'ni_current_e_addr' => {`	`'ni_current_e_addr' => {`
	`'instance_name' => 'ni_master0',`
	`'range' => 'ni_EAw-1 : 0',`
`'intfc_port' => 'current_e_addr',`	`'intfc_port' => 'current_e_addr',`
	`'type' => 'input'`
	`},`
	`'ni_current_r_addr' => {`
`'type' => 'input',`	`'type' => 'input',`
	`'intfc_port' => 'current_r_addr',`
`'instance_name' => 'ni_master0',`	`'instance_name' => 'ni_master0',`
`'intfc_name' => 'socket:ni[0]',`	`'range' => 'ni_RAw-1 : 0'`
`'range' => 'ni_EAw-1 : 0'`	`}`
	`}`
	`}`
`},`	`},`
`'uart_wb_to_jtag' => {`	`'ports' => {`
`'intfc_port' => 'jwb_o',`	`'uart_RxD_ready_sim' => {`
`'instance_name' => 'ProNoC_jtag_uart0',`	`'instance_name' => 'ProNoC_jtag_uart0',`
	`'range' => '',`
	`'intfc_name' => 'socket:RxD_sim[0]',`
`'type' => 'output',`	`'type' => 'output',`
`'range' => 'uart_WB2Jw-1 : 0',`	`'intfc_port' => 'RxD_ready_sim'`
`'intfc_name' => 'socket:jtag_to_wb[0]'`
`},`	`},`
`'ram_jtag_to_wb' => {`	`'ni_current_r_addr' => {`
`'type' => 'input',`	`'range' => 'ni_RAw-1 : 0',`
`'intfc_port' => 'jwb_i',`	`'instance_name' => 'ni_master0',`
`'instance_name' => 'single_port_ram0',`	`'intfc_port' => 'current_r_addr',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:ni[0]',`
`'range' => 'ram_J2WBw-1 : 0'`	`'type' => 'input'`
`},`	`},`
`'cpu_cpu_en' => {`	`'ni_chan_in' => {`
`'intfc_name' => 'plug:enable[0]',`	`'intfc_port' => 'chan_in',`
`'range' => '',`	`'intfc_name' => 'socket:ni[0]',`
`'intfc_port' => 'enable_i',`	`'type' => 'input',`
`'instance_name' => 'mor1kx0',`	`'range' => 'smartflit_chanel_t',`
`'type' => 'input'`	`'instance_name' => 'ni_master0'`
`}`
`}`
`}, 'ip_gen' )`
`}`
`},`	`},`
`'MEM1' => {`	`'uart_RxD_wr_sim' => {`
`'percent' => '75',`	`'intfc_port' => 'RxD_wr_sim',`
`'width' => '14'`	`'intfc_name' => 'socket:RxD_sim[0]',`
	`'type' => 'input',`
	`'instance_name' => 'ProNoC_jtag_uart0',`
	`'range' => ''`
`},`	`},`
`'SOURCE_SET' => {`	`'uart_RxD_din_sim' => {`
`'clk_number' => 1,`	`'intfc_name' => 'socket:RxD_sim[0]',`
`'reset_number' => 1,`	`'type' => 'input',`
`'reset_0_name' => 'reset',`	`'intfc_port' => 'RxD_din_sim',`
`'REDEFINE_TOP' => 0,`	`'range' => '7:0 ',`
`'clk_0_name' => 'clk',`	`'instance_name' => 'ProNoC_jtag_uart0'`
`'SOC' => bless( {`
`'gui_status' => {`
`'timeout' => 0,`
`'status' => 'ideal'`
`},`	`},`
`'hdl_files' => undef,`	`'source_reset_in' => {`
`'instances' => {`	`'instance_name' => 'clk_source0',`
`'TOP' => {`	`'range' => '',`
`'parameters_order' => [],`	`'type' => 'input',`
`'sockets' => {},`	`'intfc_name' => 'plug:reset[0]',`
`'category' => 'TOP',`	`'intfc_port' => 'reset_i'`
`'description_pdf' => undef,`
`'module' => 'TOP',`
`'plugs' => {`
`'reset' => {`
`'connection_num' => undef,`
`'value' => 1,`
`'type' => 'num',`
`'nums' => {`
`'0' => {`
`'connect_id' => 'IO',`
`'name' => 'reset',`
`'connect_socket' => undef,`
`'connect_socket_num' => undef`
`}`
`}`
`},`	`},`
`'clk' => {`	`'ram_jtag_to_wb' => {`
`'connection_num' => undef,`	`'range' => 'ram_J2WBw-1 : 0',`
`'type' => 'num',`	`'instance_name' => 'single_port_ram0',`
`'nums' => {`	`'intfc_port' => 'jwb_i',`
`'0' => {`	`'type' => 'input',`
`'name' => 'clk',`	`'intfc_name' => 'socket:jtag_to_wb[0]'`
`'connect_id' => 'IO',`
`'connect_socket' => undef,`
`'connect_socket_num' => undef`
`}`
`},`	`},`
`'value' => 1`	`'cpu_cpu_en' => {`
`}`	`'intfc_name' => 'plug:enable[0]',`
	`'intfc_port' => 'enable_i',`
	`'type' => 'input',`
	`'instance_name' => 'mor1kx0',`
	`'range' => ''`
`},`	`},`
`'module_name' => 'TOP',`	`'uart_jtag_to_wb' => {`
`'instance_name' => 'TOP'`	`'instance_name' => 'ProNoC_jtag_uart0',`
`}`	`'range' => 'uart_J2WBw-1 : 0',`
	`'type' => 'input',`
	`'intfc_port' => 'jwb_i',`
	`'intfc_name' => 'socket:jtag_to_wb[0]'`
`},`	`},`
`'instance_order' => [`	`'ram_wb_to_jtag' => {`
`'TOP'`	`'type' => 'output',`
`],`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'SOURCE_SET' => {`	`'intfc_port' => 'jwb_o',`
`'IP' => bless( {`	`'instance_name' => 'single_port_ram0',`
`'file_name' => undef,`	`'range' => 'ram_WB2Jw-1 : 0'`
`'hdl_files_ticked' => [],`
`'parameters_order' => [],`
`'GUI_REMOVE_SET' => 'DISABLE',`
`'hdl_files' => [],`
`'plugs' => {`
`'reset' => {`
`'type' => 'num',`
`'1' => {},`
`'value' => 1,`
`'0' => {`
`'name' => 'reset'`
`}`
`},`	`},`
`'clk' => {`	`'uart_wb_to_jtag' => {`
`'type' => 'num',`	`'type' => 'output',`
`'value' => 1,`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'1' => {},`	`'intfc_port' => 'jwb_o',`
`'0' => {`	`'instance_name' => 'ProNoC_jtag_uart0',`
`'name' => 'clk'`	`'range' => 'uart_WB2Jw-1 : 0'`
`}`
`}`
`},`	`},`
`'module_name' => 'TOP',`	`'source_clk_in' => {`
`'ports' => {`	`'intfc_port' => 'clk_i',`
`'clk' => {`
`'intfc_name' => 'plug:clk[0]',`	`'intfc_name' => 'plug:clk[0]',`
`'range' => undef,`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'clk_i'`	`'range' => '',`
	`'instance_name' => 'clk_source0'`
`},`	`},`
`'reset' => {`	`'ni_current_e_addr' => {`
`'intfc_port' => 'reset_i',`	`'intfc_port' => 'current_e_addr',`
	`'intfc_name' => 'socket:ni[0]',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_name' => 'plug:reset[0]',`	`'instance_name' => 'ni_master0',`
`'range' => undef`	`'range' => 'ni_EAw-1 : 0'`
`}`
`},`	`},`
`'ip_name' => 'TOP',`	`'ni_chan_out' => {`
`'ports_order' => [],`	`'type' => 'output',`
`'category' => 'TOP'`	`'intfc_port' => 'chan_out',`
`}, 'ip_gen' )`	`'intfc_name' => 'socket:ni[0]',`
	`'instance_name' => 'ni_master0',`
	`'range' => 'smartflit_chanel_t'`
	`}`
	`}`
	`}, 'ip_gen' ),`
	`'tile_nums' => [`
	`0,`
	`1,`
	`2,`
	`3`
	`]`
	`}`
`},`	`},`
`'TOP' => {`	`'MEM1' => {`
`'version' => 0`	`'width' => '14',`
	`'percent' => '75'`
`},`	`},`
`'soc_name' => {`	`'ROM0' => {`
`'TOP' => undef`	`'start' => 0,`
	`'end' => 22937`
`},`	`},`
`'device_win_adj' => {`	`'file_name' => undef,`
`'va' => '0',`	`'RAM1' => {`
`'ha' => '0'`	`'end' => 65536,`
	`'start' => 49152`
`},`	`},`
`'modules' => {}`	`'MEM3' => {`
`}, 'soc' )`	`'width' => '14',`
	`'percent' => '75'`
`},`	`},`
`'tile' => {`	`'SOURCE_SET_CONNECT' => {`
`'2' => {},`	`'T3_cs_clk_in' => 'clk',`
`'0' => {},`	`'T0_cs_reset_in' => 'reset',`
`'1' => {},`	`'T3_ss_clk_in' => 'clk0',`
`'3' => {}`	`'T0_ss_reset_in' => 'reset0',`
	`'NoC_reset' => 'reset',`
	`'T1_ss_reset_in' => 'reset0',`
	`'T2_ss_reset_in' => 'reset0',`
	`'T1_cs_reset_in' => 'reset',`
	`'T2_cs_reset_in' => 'reset',`
	`'T2_ss_clk_in' => 'clk0',`
	`'T1_ss_clk_in' => 'clk0',`
	`'T2_cs_clk_in' => 'clk',`
	`'T1_cs_clk_in' => 'clk',`
	`'T0_cs_clk_in' => 'clk',`
	`'T3_cs_reset_in' => 'reset',`
	`'T0_ss_clk_in' => 'clk0',`
	`'T3_ss_reset_in' => 'reset0',`
	`'NoC_clk' => 'clk'`
`},`	`},`
`'compile_pin_pos' => {`	`'ROM2' => {`
`'TOP_reset' => [`	`'start' => 0,`
`0,`	`'end' => 49152`
`0`
`],`
`'jtag_debug_reset_in' => [`
`0,`
`0`
`],`
`'TOP_clk' => [`
`4,`
`0`
`],`
`'processors_en' => [`
`6,`
`0`
`]`
`},`	`},`
`'current_tile_param' => undef,`	`'get_config_adj' => {`
`'gen_tiles_adj' => {`
`'ha' => '0',`	`'ha' => '0',`
`'va' => '0'`	`'va' => '0'`
`},`	`},`
`'parameters_order' => {`	`'RAM3' => {`
`'noc_param' => [`	`'end' => 65536,`
`'TOPOLOGY',`	`'start' => 49152`
`'T1',`
`'T2',`
`'T3',`
`'V',`
`'B',`
`'Fpay',`
`'ROUTE_NAME',`
`'MIN_PCK_SIZE',`
`'BYTE_EN',`
`'SSA_EN',`
`'CONGESTION_INDEX',`
`'ESCAP_VC_MASK',`
`'VC_REALLOCATION_TYPE',`
`'COMBINATION_TYPE',`
`'MUX_TYPE',`
`'C',`
`'DEBUG_EN',`
`'ADD_PIPREG_AFTER_CROSSBAR',`
`'FIRST_ARBITER_EXT_P_EN',`
`'SWA_ARBITER_TYPE',`
`'WEIGHTw',`
`'AVC_ATOMIC_EN',`
`'LB',`
`'PCK_TYPE',`
`'CAST_TYPE',`
`'SMART_MAX',`
`'SELF_LOOP_EN'`
`],`
`'SOURCE_SET' => [`
`'clk_number',`
`'clk_0_name',`
`'reset_number',`
`'reset_0_name'`
`],`
`'noc_type' => [`
`'ROUTER_TYPE'`
`],`
`'compile' => [`
`'cpu_num'`
`],`
`'SOURCE_SET_CONNECT' => [`
`'NoC_clk',`
`'T0_ss_clk_in',`
`'T1_ss_clk_in',`
`'T2_ss_clk_in',`
`'T3_ss_clk_in',`
`'NoC_reset',`
`'T0_ss_reset_in',`
`'T1_ss_reset_in',`
`'T2_ss_reset_in',`
`'T3_ss_reset_in',`
`'T0_cs_clk_in',`
`'T1_cs_clk_in',`
`'T2_cs_clk_in',`
`'T3_cs_clk_in',`
`'T0_cs_reset_in',`
`'T1_cs_reset_in',`
`'T2_cs_reset_in',`
`'T3_cs_reset_in'`
`]`
`},`	`},`
`'noc_indept_param' => {},`	`'compile_pin' => {`
`'file_name' => undef,`	`'jtag_debug_reset_in' => '*GND',`
`'noc_param' => {`	`'TOP_reset' => '*GND',`
`'VC_REALLOCATION_TYPE' => '"NONATOMIC"',`	`'TOP_clk' => 'FPGA_CLK1_50',`
`'COMBINATION_TYPE' => '"COMB_NONSPEC"',`	`'processors_en' => 'KEY'`
`'T3' => '1',`	`},`
`'ROUTE_NAME' => '"XY"',`	`'RAM0' => {`
`'C' => 0,`	`'start' => 22937,`
`'V' => '2',`	`'end' => 32768`
`'SSA_EN' => '"NO"',`	`},`
`'CONGESTION_INDEX' => 3,`	`'ROM1' => {`
`'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',`	`'end' => 49152,`
`'WEIGHTw' => '4',`	`'start' => 0`
`'DEBUG_EN' => '0',`	`},`
`'SMART_MAX' => '0',`	`'MEM0' => {`
`'SWA_ARBITER_TYPE' => '"RRA"',`	`'percent' => '70',`
`'FIRST_ARBITER_EXT_P_EN' => 1,`	`'width' => '13'`
`'SELF_LOOP_EN' => '"NO"',`	`},`
`'Fpay' => '32',`	`'compile_pin_range_lsb' => {`
`'T1' => '2',`	`'processors_en' => 0`
`'MUX_TYPE' => '"BINARY"',`
`'PCK_TYPE' => '"MULTI_FLIT"',`
`'BYTE_EN' => '1',`
`'AVC_ATOMIC_EN' => 0,`
`'MIN_PCK_SIZE' => '2',`
`'ESCAP_VC_MASK' => '2\'b01',`
`'T2' => '2',`
`'B' => '4',`
`'CAST_TYPE' => '"UNICAST"',`
`'TOPOLOGY' => '"MESH"',`
`'LB' => '4'`
`},`	`},`
`'compile_pin' => {`	`'compile' => {`
`'TOP_reset' => '*GND',`	`'type' => 'Modelsim',`
`'jtag_debug_reset_in' => '*GND',`	`'board' => 'DE10_Nano_VB2',`
`'TOP_clk' => 'FPGA_CLK1_50',`	`'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin',`
`'processors_en' => 'KEY'`	`'cpu_num' => '4',`
	`'modelsim_bin' => 'export LM_LICENSE_FILE=1717@epi03.bsc.es; /home/alireza/intelFPGA_lite/questa/questasim/bin',`
	`'compilers' => 'QuartusII,Vivado,Verilator,Modelsim'`
`},`	`},`
`'ROM2' => {`	`'tile' => {`
`'start' => 0,`	`'0' => {},`
`'end' => 49152`	`'2' => {},`
	`'1' => {},`
	`'3' => {}`
`},`	`},`
`'gui_status' => {`	`'gui_status' => {`
`'timeout' => 0,`	`'timeout' => 0,`
`'status' => 'save_project'`	`'status' => 'save_project'`
`},`	`},`
`'SOURCE_SET_CONNECT' => {`	`'SOURCE_SET' => {`
`'T2_cs_clk_in' => 'clk',`	`'reset_0_name' => 'reset',`
`'T1_cs_clk_in' => 'clk',`	`'clk_number' => 1,`
`'T0_cs_clk_in' => 'clk',`	`'reset_number' => 1,`
`'T0_ss_clk_in' => 'clk0',`	`'REDEFINE_TOP' => 0,`
`'T3_ss_clk_in' => 'clk0',`	`'clk_0_name' => 'clk',`
`'T2_ss_reset_in' => 'reset0',`	`'SOC' => bless( {`
`'T2_cs_reset_in' => 'reset',`	`'TOP' => {`
`'T0_ss_reset_in' => 'reset0',`	`'version' => 0`
`'T1_ss_clk_in' => 'clk0',`	`},`
`'T3_cs_clk_in' => 'clk',`	`'hdl_files' => undef,`
`'T3_cs_reset_in' => 'reset',`	`'instance_order' => [`
`'T1_ss_reset_in' => 'reset0',`	`'TOP'`
`'T2_ss_clk_in' => 'clk0',`	`],`
`'T0_cs_reset_in' => 'reset',`	`'instances' => {`
`'NoC_clk' => 'clk',`	`'TOP' => {`
`'T1_cs_reset_in' => 'reset',`	`'module_name' => 'TOP',`
`'T3_ss_reset_in' => 'reset0',`	`'category' => 'TOP',`
`'NoC_reset' => 'reset'`	`'plugs' => {`
	`'clk' => {`
	`'connection_num' => undef,`
	`'nums' => {`
	`'0' => {`
	`'connect_id' => 'IO',`
	`'connect_socket_num' => undef,`
	`'name' => 'clk',`
	`'connect_socket' => undef`
	`}`
	`},`
	`'value' => 1,`
	`'type' => 'num'`
	`},`
	`'reset' => {`
	`'nums' => {`
	`'0' => {`
	`'connect_socket_num' => undef,`
	`'connect_id' => 'IO',`
	`'connect_socket' => undef,`
	`'name' => 'reset'`
	`}`
	`},`
	`'connection_num' => undef,`
	`'value' => 1,`
	`'type' => 'num'`
	`}`
	`},`
	`'description_pdf' => undef,`
	`'instance_name' => 'TOP',`
	`'parameters_order' => [],`
	`'module' => 'TOP',`
	`'sockets' => {}`
	`}`
	`},`
	`'modules' => {},`
	`'soc_name' => {`
	`'TOP' => undef`
	`},`
	`'SOURCE_SET' => {`
	`'IP' => bless( {`
	`'ip_name' => 'TOP',`
	`'ports_order' => [],`
	`'ports' => {`
	`'reset' => {`
	`'range' => undef,`
	`'type' => 'input',`
	`'intfc_port' => 'reset_i',`
	`'intfc_name' => 'plug:reset[0]'`
	`},`
	`'clk' => {`
	`'intfc_name' => 'plug:clk[0]',`
	`'intfc_port' => 'clk_i',`
	`'type' => 'input',`
	`'range' => undef`
	`}`
	`},`
	`'file_name' => undef,`
	`'hdl_files_ticked' => [],`
	`'parameters_order' => [],`
	`'GUI_REMOVE_SET' => 'DISABLE',`
	`'module_name' => 'TOP',`
	`'category' => 'TOP',`
	`'hdl_files' => [],`
	`'plugs' => {`
	`'reset' => {`
	`'1' => {},`
	`'type' => 'num',`
	`'value' => 1,`
	`'0' => {`
	`'name' => 'reset'`
	`}`
	`},`
	`'clk' => {`
	`'1' => {},`
	`'type' => 'num',`
	`'value' => 1,`
	`'0' => {`
	`'name' => 'clk'`
	`}`
	`}`
	`}`
	`}, 'ip_gen' )`
	`},`
	`'device_win_adj' => {`
	`'va' => '0',`
	`'ha' => '0'`
	`},`
	`'gui_status' => {`
	`'status' => 'ideal',`
	`'timeout' => 0`
	`}`
	`}, 'soc' )`
	`},`
	`'noc_indept_param' => {},`
	`'verilator' => {`
	`'libs' => {`
	`'Vtile1' => '--top-module tile_1',`
	`'Vtile3' => '--top-module tile_3',`
	`'Vtile0' => '--top-module tile_0',`
	`'Vrouter1' => '--top-module router_top_v -GP=5 ',`
	`'Vtile2' => '--top-module tile_2'`
	`}`
	`},`
	`'soc_param' => {`
	`'default' => {`
	`'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
	`'uart_JINDEXw' => '8',`
	`'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
	`'uart_JTAG_INDEX' => '126-CORE_ID',`
	`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
	`'ram_JDw' => 'ram_Dw',`
	`'uart_JTAG_CHAIN' => '3',`
	`'ram_JTAG_CHAIN' => '4',`
	`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`
	`'ram_JTAG_INDEX' => 'CORE_ID',`
	`'uart_JAw' => '32',`
	`'uart_JDw' => '32',`
	`'ram_Aw' => '14',`
	`'ram_JAw' => '32',`
	`'uart_JSTATUSw' => '8',`
	`'ram_JSTATUSw' => '8',`
	`'ram_Dw' => '32',`
	`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
	`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
	`'ram_JINDEXw' => '8'`
	`}`
`},`	`},`
	`'current_tile_param' => undef,`
`'compile_pin_range_hsb' => {},`	`'compile_pin_range_hsb' => {},`
	`'mpsoc_name' => 'mor1k_mpsoc',`
	`'gen_tiles_adj' => {`
	`'va' => '0',`
	`'ha' => '0'`
	`},`
`'setting' => {`	`'setting' => {`
`'show_adv_setting' => 0,`
`'show_noc_setting' => 1,`	`'show_noc_setting' => 1,`
	`'show_adv_setting' => 0,`
`'show_tile_setting' => 1,`	`'show_tile_setting' => 1,`
`'soc_path' => 'lib/soc'`	`'soc_path' => 'lib/soc'`
`},`	`},`
`'RAM2' => {`
`'start' => 49152,`
`'end' => 65536`
`},`
`'top_ip' => bless( {`	`'top_ip' => bless( {`
`'ports' => {`	`'ports' => {`
`'T2_uart_wb_to_jtag' => {`
`'range' => 'T2_uart_WB2Jw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'instance_name' => 'T2',`
`'intfc_port' => 'jwb_o',`
`'type' => 'output'`
`},`
`'T1_uart_jtag_to_wb' => {`	`'T1_uart_jtag_to_wb' => {`
	`'instance_name' => 'T1',`
`'range' => 'T1_uart_J2WBw-1 : 0',`	`'range' => 'T1_uart_J2WBw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_port' => 'jwb_i',`
`'type' => 'input',`	`'type' => 'input',`
`'instance_name' => 'T1',`	`'intfc_name' => 'socket:jtag_to_wb[0]'`
`'intfc_port' => 'jwb_i'`
`},`	`},`
`'clk' => {`	`'T2_ram_jtag_to_wb' => {`
`'intfc_name' => 'plug:clk[0]',`	`'type' => 'input',`
`'range' => '',`	`'intfc_port' => 'jwb_i',`
`'intfc_port' => 'clk_i',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'instance_name' => 'IO',`	`'instance_name' => 'T2',`
`'type' => 'input'`	`'range' => 'T2_ram_J2WBw-1 : 0'`
`},`	`},`
`'T3_ram_wb_to_jtag' => {`	`'T3_ram_wb_to_jtag' => {`
`'instance_name' => 'T3',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'type' => 'output',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'type' => 'output',`
	`'instance_name' => 'T3',`
`'range' => 'T3_ram_WB2Jw-1 : 0'`	`'range' => 'T3_ram_WB2Jw-1 : 0'`
`},`	`},`
`'T3_ram_jtag_to_wb' => {`	`'T1_ram_jtag_to_wb' => {`
`'range' => 'T3_ram_J2WBw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'instance_name' => 'T3',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
`'type' => 'input'`	`'type' => 'input',`
`},`
`'T1_uart_wb_to_jtag' => {`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T1_uart_WB2Jw-1 : 0',`
`'type' => 'output',`
`'instance_name' => 'T1',`	`'instance_name' => 'T1',`
`'intfc_port' => 'jwb_o'`	`'range' => 'T1_ram_J2WBw-1 : 0'`
	`},`
	`'T2_uart_jtag_to_wb' => {`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'intfc_port' => 'jwb_i',`
	`'type' => 'input',`
	`'instance_name' => 'T2',`
	`'range' => 'T2_uart_J2WBw-1 : 0'`
	`},`
	`'clk' => {`
	`'type' => 'input',`
	`'intfc_port' => 'clk_i',`
	`'intfc_name' => 'plug:clk[0]',`
	`'range' => '',`
	`'instance_name' => 'IO'`
`},`	`},`
`'T3_uart_wb_to_jtag' => {`	`'T3_uart_wb_to_jtag' => {`
`'instance_name' => 'T3',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'type' => 'output',`	`'type' => 'output',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'instance_name' => 'T3',`
`'range' => 'T3_uart_WB2Jw-1 : 0'`	`'range' => 'T3_uart_WB2Jw-1 : 0'`
`},`	`},`
	`'T0_ram_jtag_to_wb' => {`
	`'intfc_port' => 'jwb_i',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'type' => 'input',`
	`'instance_name' => 'T0',`
	`'range' => 'T0_ram_J2WBw-1 : 0'`
	`},`
	`'T0_uart_jtag_to_wb' => {`
	`'intfc_port' => 'jwb_i',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'type' => 'input',`
	`'instance_name' => 'T0',`
	`'range' => 'T0_uart_J2WBw-1 : 0'`
	`},`
`'processors_en' => {`	`'processors_en' => {`
`'intfc_name' => 'plug:enable[0]',`
`'range' => '',`
`'instance_name' => 'IO',`
`'intfc_port' => 'enable_i',`	`'intfc_port' => 'enable_i',`
`'type' => 'input'`	`'intfc_name' => 'plug:enable[0]',`
	`'type' => 'input',`
	`'range' => '',`
	`'instance_name' => 'IO'`
`},`	`},`
`'reset' => {`	`'reset' => {`
	`'intfc_name' => 'plug:reset[0]',`
	`'intfc_port' => 'reset_i',`
`'type' => 'input',`	`'type' => 'input',`
`'instance_name' => 'IO',`	`'instance_name' => 'IO',`
`'intfc_port' => 'reset_i',`
`'intfc_name' => 'plug:reset[0]',`
`'range' => ''`	`'range' => ''`
`},`	`},`
`'T0_ram_jtag_to_wb' => {`	`'T2_ram_wb_to_jtag' => {`
`'range' => 'T0_ram_J2WBw-1 : 0',`	`'intfc_port' => 'jwb_o',`
	`'type' => 'output',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'intfc_port' => 'jwb_i',`	`'range' => 'T2_ram_WB2Jw-1 : 0',`
`'instance_name' => 'T0',`	`'instance_name' => 'T2'`
`'type' => 'input'`
`},`	`},`
`'T0_uart_jtag_to_wb' => {`	`'T3_ram_jtag_to_wb' => {`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T0_uart_J2WBw-1 : 0',`	`'intfc_port' => 'jwb_i',`
`'instance_name' => 'T0',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'jwb_i'`	`'instance_name' => 'T3',`
	`'range' => 'T3_ram_J2WBw-1 : 0'`
`},`	`},`
`'T1_ram_jtag_to_wb' => {`	`'T0_uart_wb_to_jtag' => {`
	`'instance_name' => 'T0',`
	`'range' => 'T0_uart_WB2Jw-1 : 0',`
	`'intfc_port' => 'jwb_o',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T1_ram_J2WBw-1 : 0',`	`'type' => 'output'`
`'type' => 'input',`
`'instance_name' => 'T1',`
`'intfc_port' => 'jwb_i'`
`},`	`},`
`'T3_uart_jtag_to_wb' => {`	`'T3_uart_jtag_to_wb' => {`
`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T3_uart_J2WBw-1 : 0',`
`'intfc_port' => 'jwb_i',`
`'instance_name' => 'T3',`	`'instance_name' => 'T3',`
`'type' => 'input'`	`'range' => 'T3_uart_J2WBw-1 : 0',`
`},`
`'T2_uart_jtag_to_wb' => {`
`'instance_name' => 'T2',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]'`
`'range' => 'T2_uart_J2WBw-1 : 0'`
`},`
`'T2_ram_jtag_to_wb' => {`
`'range' => 'T2_ram_J2WBw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'instance_name' => 'T2',`
`'type' => 'input',`
`'intfc_port' => 'jwb_i'`
`},`	`},`
`'T1_ram_wb_to_jtag' => {`	`'T1_ram_wb_to_jtag' => {`
	`'range' => 'T1_ram_WB2Jw-1 : 0',`
`'instance_name' => 'T1',`	`'instance_name' => 'T1',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'type' => 'output',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T1_ram_WB2Jw-1 : 0',`	`'type' => 'output'`
`'intfc_name' => 'socket:jtag_to_wb[0]'`
`},`	`},`
`'T0_ram_wb_to_jtag' => {`	`'T0_ram_wb_to_jtag' => {`
	`'type' => 'output',`
	`'intfc_port' => 'jwb_o',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T0_ram_WB2Jw-1 : 0',`	`'range' => 'T0_ram_WB2Jw-1 : 0',`
	`'instance_name' => 'T0'`
	`},`
	`'T2_uart_wb_to_jtag' => {`
	`'range' => 'T2_uart_WB2Jw-1 : 0',`
	`'instance_name' => 'T2',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'instance_name' => 'T0',`
`'type' => 'output'`	`'type' => 'output'`
`},`	`},`
`'T0_uart_wb_to_jtag' => {`	`'T1_uart_wb_to_jtag' => {`
	`'instance_name' => 'T1',`
	`'range' => 'T1_uart_WB2Jw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T0_uart_WB2Jw-1 : 0',`
`'type' => 'output',`
`'instance_name' => 'T0',`
`'intfc_port' => 'jwb_o'`
`},`
`'T2_ram_wb_to_jtag' => {`
`'type' => 'output',`
`'instance_name' => 'T2',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'range' => 'T2_ram_WB2Jw-1 : 0',`	`'type' => 'output'`
`'intfc_name' => 'socket:jtag_to_wb[0]'`
`}`	`}`
`},`	`},`
`'interface' => {`	`'interface' => {`
`'plug:clk[0]' => {`	`'socket:jtag_to_wb[0]' => {`
`'ports' => {`	`'ports' => {`
`'clk' => {`	`'T0_ram_jtag_to_wb' => {`
`'intfc_port' => 'clk_i',`
`'instance_name' => 'IO',`
`'type' => 'input',`	`'type' => 'input',`
`'range' => ''`	`'intfc_port' => 'jwb_i',`
`}`	`'instance_name' => 'T0',`
`}`	`'range' => 'T0_ram_J2WBw-1 : 0'`
`},`	`},`
`'plug:reset[0]' => {`	`'T3_uart_wb_to_jtag' => {`
`'ports' => {`	`'instance_name' => 'T3',`
`'reset' => {`	`'range' => 'T3_uart_WB2Jw-1 : 0',`
`'range' => '',`	`'intfc_port' => 'jwb_o',`
`'type' => 'input',`	`'type' => 'output'`
`'intfc_port' => 'reset_i',`
`'instance_name' => 'IO'`
`}`
`}`
`},`	`},`
`'socket:jtag_to_wb[0]' => {`
`'ports' => {`
`'T0_uart_jtag_to_wb' => {`	`'T0_uart_jtag_to_wb' => {`
`'intfc_port' => 'jwb_i',`
`'instance_name' => 'T0',`	`'instance_name' => 'T0',`
`'type' => 'input',`	`'range' => 'T0_uart_J2WBw-1 : 0',`
`'range' => 'T0_uart_J2WBw-1 : 0'`
`},`
`'T0_ram_jtag_to_wb' => {`
`'range' => 'T0_ram_J2WBw-1 : 0',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
`'type' => 'input',`	`'type' => 'input'`
`'instance_name' => 'T0'`
`},`	`},`
`'T3_uart_jtag_to_wb' => {`	`'T3_ram_wb_to_jtag' => {`
`'range' => 'T3_uart_J2WBw-1 : 0',`	`'intfc_port' => 'jwb_o',`
	`'type' => 'output',`
	`'instance_name' => 'T3',`
	`'range' => 'T3_ram_WB2Jw-1 : 0'`
	`},`
	`'T2_ram_jtag_to_wb' => {`
	`'instance_name' => 'T2',`
	`'range' => 'T2_ram_J2WBw-1 : 0',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
	`'type' => 'input'`
	`},`
	`'T1_uart_jtag_to_wb' => {`
	`'range' => 'T1_uart_J2WBw-1 : 0',`
	`'instance_name' => 'T1',`
`'type' => 'input',`	`'type' => 'input',`
`'instance_name' => 'T3'`	`'intfc_port' => 'jwb_i'`
`},`	`},`
`'T2_uart_jtag_to_wb' => {`	`'T2_uart_jtag_to_wb' => {`
`'range' => 'T2_uart_J2WBw-1 : 0',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
`'instance_name' => 'T2'`	`'instance_name' => 'T2',`
	`'range' => 'T2_uart_J2WBw-1 : 0'`
`},`	`},`
`'T1_ram_jtag_to_wb' => {`	`'T1_ram_jtag_to_wb' => {`
`'type' => 'input',`
`'intfc_port' => 'jwb_i',`
`'instance_name' => 'T1',`	`'instance_name' => 'T1',`
`'range' => 'T1_ram_J2WBw-1 : 0'`	`'range' => 'T1_ram_J2WBw-1 : 0',`
	`'type' => 'input',`
	`'intfc_port' => 'jwb_i'`
`},`	`},`
`'T2_ram_jtag_to_wb' => {`	`'T2_uart_wb_to_jtag' => {`
`'range' => 'T2_ram_J2WBw-1 : 0',`
`'intfc_port' => 'jwb_i',`
`'instance_name' => 'T2',`	`'instance_name' => 'T2',`
`'type' => 'input'`	`'range' => 'T2_uart_WB2Jw-1 : 0',`
`},`
`'T1_ram_wb_to_jtag' => {`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'instance_name' => 'T1',`	`'type' => 'output'`
`'type' => 'output',`
`'range' => 'T1_ram_WB2Jw-1 : 0'`
`},`	`},`
`'T0_ram_wb_to_jtag' => {`	`'T0_ram_wb_to_jtag' => {`
`'range' => 'T0_ram_WB2Jw-1 : 0',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'type' => 'output',`	`'type' => 'output',`
	`'range' => 'T0_ram_WB2Jw-1 : 0',`
`'instance_name' => 'T0'`	`'instance_name' => 'T0'`
`},`	`},`
`'T0_uart_wb_to_jtag' => {`	`'T1_uart_wb_to_jtag' => {`
`'type' => 'output',`
`'intfc_port' => 'jwb_o',`
`'instance_name' => 'T0',`
`'range' => 'T0_uart_WB2Jw-1 : 0'`
`},`
`'T2_ram_wb_to_jtag' => {`
`'range' => 'T2_ram_WB2Jw-1 : 0',`
`'type' => 'output',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'instance_name' => 'T2'`
`},`
`'T2_uart_wb_to_jtag' => {`
`'type' => 'output',`	`'type' => 'output',`
`'intfc_port' => 'jwb_o',`	`'instance_name' => 'T1',`
`'instance_name' => 'T2',`	`'range' => 'T1_uart_WB2Jw-1 : 0'`
`'range' => 'T2_uart_WB2Jw-1 : 0'`
`},`	`},`
`'T1_uart_jtag_to_wb' => {`	`'T3_ram_jtag_to_wb' => {`
`'type' => 'input',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
`'instance_name' => 'T1',`	`'type' => 'input',`
`'range' => 'T1_uart_J2WBw-1 : 0'`	`'range' => 'T3_ram_J2WBw-1 : 0',`
	`'instance_name' => 'T3'`
`},`	`},`
`'T3_ram_wb_to_jtag' => {`	`'T2_ram_wb_to_jtag' => {`
`'range' => 'T3_ram_WB2Jw-1 : 0',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'instance_name' => 'T3',`	`'type' => 'output',`
`'type' => 'output'`	`'range' => 'T2_ram_WB2Jw-1 : 0',`
	`'instance_name' => 'T2'`
`},`	`},`
`'T3_uart_wb_to_jtag' => {`	`'T0_uart_wb_to_jtag' => {`
	`'instance_name' => 'T0',`
	`'range' => 'T0_uart_WB2Jw-1 : 0',`
`'type' => 'output',`	`'type' => 'output',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o'`
`'instance_name' => 'T3',`
`'range' => 'T3_uart_WB2Jw-1 : 0'`
`},`	`},`
`'T1_uart_wb_to_jtag' => {`	`'T1_ram_wb_to_jtag' => {`
`'instance_name' => 'T1',`	`'instance_name' => 'T1',`
`'intfc_port' => 'jwb_o',`	`'range' => 'T1_ram_WB2Jw-1 : 0',`
`'type' => 'output',`	`'type' => 'output',`
`'range' => 'T1_uart_WB2Jw-1 : 0'`	`'intfc_port' => 'jwb_o'`
`},`	`},`
`'T3_ram_jtag_to_wb' => {`	`'T3_uart_jtag_to_wb' => {`
`'range' => 'T3_ram_J2WBw-1 : 0',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
	`'range' => 'T3_uart_J2WBw-1 : 0',`
`'instance_name' => 'T3'`	`'instance_name' => 'T3'`
`}`	`}`
`}`	`}`
`},`	`},`
`'plug:enable[0]' => {`	`'plug:enable[0]' => {`
`'ports' => {`	`'ports' => {`
`'processors_en' => {`	`'processors_en' => {`
	`'instance_name' => 'IO',`
	`'range' => '',`
	`'intfc_port' => 'enable_i',`
	`'type' => 'input'`
	`}`
	`}`
	`},`
	`'plug:clk[0]' => {`
	`'ports' => {`
	`'clk' => {`
	`'range' => '',`
	`'instance_name' => 'IO',`
	`'intfc_port' => 'clk_i',`
	`'type' => 'input'`
	`}`
	`}`
	`},`
	`'plug:reset[0]' => {`
	`'ports' => {`
	`'reset' => {`
	`'intfc_port' => 'reset_i',`
	`'type' => 'input',`
	`'instance_name' => 'IO',`
	`'range' => ''`
	`}`
	`}`
	`}`
	`},`
	`'instance_ids' => {`
	`'T2' => {`
	`'ports' => {`
	`'T2_ram_wb_to_jtag' => {`
	`'range' => 'T2_ram_WB2Jw-1 : 0',`
	`'intfc_port' => 'jwb_o',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'type' => 'output'`
	`},`
	`'T2_ram_jtag_to_wb' => {`
	`'intfc_port' => 'jwb_i',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'type' => 'input',`
	`'range' => 'T2_ram_J2WBw-1 : 0'`
	`},`
	`'T2_uart_wb_to_jtag' => {`
	`'type' => 'output',`
	`'intfc_port' => 'jwb_o',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'range' => 'T2_uart_WB2Jw-1 : 0'`
	`},`
	`'T2_uart_jtag_to_wb' => {`
	`'intfc_port' => 'jwb_i',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'enable_i',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'instance_name' => 'IO',`	`'range' => 'T2_uart_J2WBw-1 : 0'`
`'range' => ''`
`}`
`}`	`}`
`}`	`}`
`},`	`},`
`'instance_ids' => {`
`'IO' => {`	`'IO' => {`
`'ports' => {`	`'ports' => {`
`'reset' => {`	`'reset' => {`
`'intfc_name' => 'plug:reset[0]',`
`'range' => '',`
`'intfc_port' => 'reset_i',`	`'intfc_port' => 'reset_i',`
`'type' => 'input'`	`'intfc_name' => 'plug:reset[0]',`
	`'type' => 'input',`
	`'range' => ''`
`},`	`},`
`'processors_en' => {`	`'processors_en' => {`
	`'range' => '',`
`'intfc_port' => 'enable_i',`	`'intfc_port' => 'enable_i',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_name' => 'plug:enable[0]',`	`'intfc_name' => 'plug:enable[0]'`
`'range' => ''`
`},`	`},`
`'clk' => {`	`'clk' => {`
`'range' => '',`	`'range' => '',`
`'intfc_name' => 'plug:clk[0]',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'clk_i'`	`'intfc_port' => 'clk_i',`
	`'intfc_name' => 'plug:clk[0]'`
`}`	`}`
`}`	`}`
`},`	`},`
`'T0' => {`	`'T1' => {`
`'ports' => {`	`'ports' => {`
`'T0_uart_wb_to_jtag' => {`	`'T1_ram_wb_to_jtag' => {`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T0_uart_WB2Jw-1 : 0',`	`'intfc_port' => 'jwb_o',`
`'type' => 'output',`	`'type' => 'output',`
`'intfc_port' => 'jwb_o'`	`'range' => 'T1_ram_WB2Jw-1 : 0'`
`},`
`'T0_uart_jtag_to_wb' => {`
`'type' => 'input',`
`'intfc_port' => 'jwb_i',`
`'range' => 'T0_uart_J2WBw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]'`
`},`	`},`
`'T0_ram_wb_to_jtag' => {`	`'T1_uart_wb_to_jtag' => {`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'range' => 'T1_uart_WB2Jw-1 : 0',`
`'range' => 'T0_ram_WB2Jw-1 : 0',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'type' => 'output'`	`'type' => 'output'`
`},`	`},`
`'T0_ram_jtag_to_wb' => {`	`'T1_ram_jtag_to_wb' => {`
`'type' => 'input',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
`'range' => 'T0_ram_J2WBw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]'`
`}`
`}`
`},`
`'T3' => {`
`'ports' => {`
`'T3_ram_wb_to_jtag' => {`
`'type' => 'output',`
`'intfc_port' => 'jwb_o',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T3_ram_WB2Jw-1 : 0'`
`},`
`'T3_uart_jtag_to_wb' => {`
`'intfc_port' => 'jwb_i',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'range' => 'T1_ram_J2WBw-1 : 0'`
`'range' => 'T3_uart_J2WBw-1 : 0'`
`},`	`},`
`'T3_uart_wb_to_jtag' => {`	`'T1_uart_jtag_to_wb' => {`
`'type' => 'output',`
`'intfc_port' => 'jwb_o',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T3_uart_WB2Jw-1 : 0'`
`},`
`'T3_ram_jtag_to_wb' => {`
`'type' => 'input',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'type' => 'input',`
`'range' => 'T3_ram_J2WBw-1 : 0'`	`'range' => 'T1_uart_J2WBw-1 : 0'`
`}`	`}`
`}`	`}`
`},`	`},`
`'T1' => {`	`'T0' => {`
`'ports' => {`	`'ports' => {`
`'T1_ram_wb_to_jtag' => {`	`'T0_ram_wb_to_jtag' => {`
`'type' => 'output',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'range' => 'T1_ram_WB2Jw-1 : 0',`	`'type' => 'output',`
`'intfc_name' => 'socket:jtag_to_wb[0]'`	`'range' => 'T0_ram_WB2Jw-1 : 0'`
`},`	`},`
`'T1_uart_jtag_to_wb' => {`	`'T0_uart_jtag_to_wb' => {`
`'intfc_port' => 'jwb_i',`	`'range' => 'T0_uart_J2WBw-1 : 0',`
`'type' => 'input',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T1_uart_J2WBw-1 : 0'`	`'intfc_port' => 'jwb_i',`
	`'type' => 'input'`
`},`	`},`
`'T1_uart_wb_to_jtag' => {`	`'T0_uart_wb_to_jtag' => {`
`'range' => 'T1_uart_WB2Jw-1 : 0',`	`'intfc_port' => 'jwb_o',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'type' => 'output',`	`'type' => 'output',`
`'intfc_port' => 'jwb_o'`	`'range' => 'T0_uart_WB2Jw-1 : 0'`
`},`	`},`
`'T1_ram_jtag_to_wb' => {`	`'T0_ram_jtag_to_wb' => {`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T1_ram_J2WBw-1 : 0'`	`'range' => 'T0_ram_J2WBw-1 : 0'`
`}`	`}`
`}`	`}`
`},`	`},`
`'T2' => {`	`'T3' => {`
`'ports' => {`	`'ports' => {`
`'T2_ram_wb_to_jtag' => {`	`'T3_ram_wb_to_jtag' => {`
	`'range' => 'T3_ram_WB2Jw-1 : 0',`
`'type' => 'output',`	`'type' => 'output',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'range' => 'T2_ram_WB2Jw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]'`	`'intfc_name' => 'socket:jtag_to_wb[0]'`
`},`	`},`
`'T2_uart_jtag_to_wb' => {`	`'T3_uart_wb_to_jtag' => {`
`'range' => 'T2_uart_J2WBw-1 : 0',`	`'range' => 'T3_uart_WB2Jw-1 : 0',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'intfc_port' => 'jwb_o',`
	`'type' => 'output'`
	`},`
	`'T3_ram_jtag_to_wb' => {`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
`'type' => 'input'`	`'type' => 'input',`
	`'range' => 'T3_ram_J2WBw-1 : 0'`
`},`	`},`
`'T2_ram_jtag_to_wb' => {`	`'T3_uart_jtag_to_wb' => {`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T2_ram_J2WBw-1 : 0'`	`'range' => 'T3_uart_J2WBw-1 : 0'`
`},`
`'T2_uart_wb_to_jtag' => {`
`'intfc_port' => 'jwb_o',`
`'type' => 'output',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'T2_uart_WB2Jw-1 : 0'`
`}`	`}`
`}`	`}`
`}`	`}`
`}`	`}`
`}, 'ip_gen' ),`	`}, 'ip_gen' ),`
`'ROM0' => {`
`'start' => 0,`
`'end' => 22937`
`},`
`'soc_param' => {`
`'default' => {`
`'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
`'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
`'uart_JSTATUSw' => '8',`
`'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',`
`'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`
`'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
`'ram_Aw' => '14',`
`'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
`'uart_JDw' => '32',`
`'ram_JSTATUSw' => '8',`
`'ram_JINDEXw' => '8',`
`'uart_JTAG_INDEX' => '126-CORE_ID',`
`'ram_JAw' => '32',`
`'ram_JTAG_INDEX' => 'CORE_ID',`
`'ram_Dw' => '32',`
`'uart_JAw' => '32',`
`'ram_JTAG_CHAIN' => '4',`
`'uart_JINDEXw' => '8',`
`'ram_JDw' => 'ram_Dw',`
`'uart_JTAG_CHAIN' => '3'`
`}`
`},`
`'verilator' => {`
`'libs' => {`
`'Vtile3' => '--top-module tile_3',`
`'Vtile0' => '--top-module tile_0',`
`'Vrouter1' => '--top-module router_top_v -GP=5 ',`
`'Vtile1' => '--top-module tile_1',`
`'Vtile2' => '--top-module tile_2'`
`}`
`},`
`'JTAG' => {`	`'JTAG' => {`
`'M_CHAIN' => 4`	`'M_CHAIN' => 4`
`},`	`},`
`'get_config_adj' => {`	`'parameters_order' => {`
`'va' => '0',`	`'compile' => [`
`'ha' => '0'`	`'cpu_num'`
`},`	`],`
`'MEM0' => {`	`'SOURCE_SET_CONNECT' => [`
`'percent' => '70',`	`'NoC_clk',`
`'width' => '13'`	`'T0_ss_clk_in',`
`},`	`'T1_ss_clk_in',`
`'RAM1' => {`	`'T2_ss_clk_in',`
`'end' => 65536,`	`'T3_ss_clk_in',`
`'start' => 49152`	`'NoC_reset',`
`},`	`'T0_ss_reset_in',`
`'MEM3' => {`	`'T1_ss_reset_in',`
`'width' => '14',`	`'T2_ss_reset_in',`
`'percent' => '75'`	`'T3_ss_reset_in',`
`},`	`'T0_cs_clk_in',`
`'ROM1' => {`	`'T1_cs_clk_in',`
`'end' => 49152,`	`'T2_cs_clk_in',`
`'start' => 0`	`'T3_cs_clk_in',`
`},`	`'T0_cs_reset_in',`
`'compile_assign_type' => {`	`'T1_cs_reset_in',`
`'TOP_reset' => 'Direct',`	`'T2_cs_reset_in',`
`'jtag_debug_reset_in' => 'Direct',`	`'T3_cs_reset_in'`
`'processors_en' => 'Direct',`	`],`
`'TOP_clk' => 'Direct'`	`'noc_param' => [`
`},`	`'TOPOLOGY',`
`'noc_type' => {`	`'T1',`
`'ROUTER_TYPE' => '"VC_BASED"'`	`'T2',`
	`'T3',`
	`'V',`
	`'B',`
	`'Fpay',`
	`'ROUTE_NAME',`
	`'MIN_PCK_SIZE',`
	`'BYTE_EN',`
	`'SSA_EN',`
	`'CONGESTION_INDEX',`
	`'ESCAP_VC_MASK',`
	`'VC_REALLOCATION_TYPE',`
	`'COMBINATION_TYPE',`
	`'MUX_TYPE',`
	`'C',`
	`'DEBUG_EN',`
	`'ADD_PIPREG_AFTER_CROSSBAR',`
	`'FIRST_ARBITER_EXT_P_EN',`
	`'SWA_ARBITER_TYPE',`
	`'WEIGHTw',`
	`'AVC_ATOMIC_EN',`
	`'LB',`
	`'PCK_TYPE',`
	`'CAST_TYPE',`
	`'SMART_MAX',`
	`'SELF_LOOP_EN',`
	`'MCAST_ENDP_LIST'`
	`],`
	`'SOURCE_SET' => [`
	`'clk_number',`
	`'clk_0_name',`
	`'reset_number',`
	`'reset_0_name'`
	`],`
	`'noc_type' => [`
	`'ROUTER_TYPE'`
	`]`
`},`	`},`
`'liststore' => {`	`'liststore' => {`
`'ha' => '0',`	`'va' => '0',`
`'va' => '0'`	`'ha' => '0'`
`},`
`'fpga_param' => {},`
`'RAM0' => {`
`'end' => 32768,`
`'start' => 22937`
`}`	`}`
`}, 'mpsoc' );`	`}, 'mpsoc' );`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [mpsoc/] [mor1k_mpsoc.MPSOC] - Diff between revs 54 and 56