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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [soc/] [mor1k_tile.SOC] - Diff between revs 54 and 56

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`#######################################################################`	`#######################################################################`
`## File: mor1k_tile.SOC`	`## File: mor1k_tile.SOC`
`##`	`##`
`## Copyright (C) 2014-2019 Alireza Monemi`	`## Copyright (C) 2014-2021 Alireza Monemi`
`##`	`##`
`## This file is part of ProNoC 1.9.1`	`## This file is part of ProNoC 2.1.0`
`##`	`##`
`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`	`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
`## MAY CAUSE UNEXPECTED BEHAVIOR.`	`## MAY CAUSE UNEXPECTED BEHAVIOR.`
`################################################################################`	`################################################################################`

`$soc = bless( {`	`$soc = bless( {`
`'timer0' => {`	`'device_win_adj' => {`
`'version' => 12`	`'va' => '0',`
`},`	`'ha' => '0'`
`'current_module_param_type' => undef,`
`'SOURCE_SET' => {`
`'SOC' => bless( {`
`'modules' => {},`
`'hdl_files_ticked' => undef,`
`'SOURCE_SET' => {`
`'IP' => bless( {`
`'parameters_order' => [],`
`'hdl_files' => [],`
`'GUI_REMOVE_SET' => 'DISABLE',`
`'file_name' => undef,`
`'hdl_files_ticked' => [],`
`'category' => 'TOP',`
`'ports' => {`
`'source_clk_in' => {`
`'range' => undef,`
`'intfc_name' => 'plug:clk[0]',`
`'type' => 'input',`
`'intfc_port' => 'clk_i'`
`},`
`'source_reset_in' => {`
`'intfc_port' => 'reset_i',`
`'type' => 'input',`
`'intfc_name' => 'plug:reset[0]',`
`'range' => undef`
`}`
`},`
`'plugs' => {`
`'reset' => {`
`'1' => {},`
`'0' => {`
`'name' => 'source_reset_in'`
`},`
`'value' => 1,`
`'type' => 'num'`
`},`
`'clk' => {`
`'value' => 1,`
`'0' => {`
`'name' => 'source_clk_in'`
`},`
`'1' => {},`
`'type' => 'num'`
`}`
`},`
`'module_name' => 'TOP',`
`'ip_name' => 'TOP',`
`'ports_order' => []`
`}, 'ip_gen' )`
`},`
`'soc_name' => {`
`'TOP' => undef`
`},`
`'TOP' => {`
`'version' => 0`
`},`
`'hdl_files' => undef,`
`'gui_status' => {`
`'status' => 'refresh_soc',`
`'timeout' => 0`
`},`
`'instances' => {`
`'TOP' => {`
`'instance_name' => 'TOP',`
`'plugs' => {`
`'reset' => {`
`'connection_num' => undef,`
`'nums' => {`
`'0' => {`
`'connect_socket_num' => undef,`
`'connect_socket' => undef,`
`'name' => 'source_reset_in',`
`'connect_id' => 'IO'`
`}`
`},`
`'type' => 'num',`
`'value' => 1`
`},`	`},`
`'clk' => {`	`'global_param' => {`
`'connection_num' => undef,`	`'CORE_ID' => 3,`
`'value' => 1,`	`'SW_LOC' => '/home/alireza/work/git/hca_git/mpsoc_work/SOC/mor1k_tile/sw'`
`'nums' => {`
`'0' => {`
`'connect_socket' => undef,`
`'connect_socket_num' => undef,`
`'connect_id' => 'IO',`
`'name' => 'source_clk_in'`
`}`
`},`	`},`
`'type' => 'num'`	`'graph_save' => {},`
`}`	`'current_module_param' => undef,`
	`'compile_pin_pos' => {},`
	`'modules' => {},`
	`'soc_name' => 'mor1k_tile',`
	`'Unset-intfc' => {},`
	`'tile_diagram' => {`
	`'show_unused' => 1,`
	`'show_clk' => 0,`
	`'show_reset' => 0`
`},`	`},`
`'module_name' => 'TOP',`	`'mor1kx0' => {`
`'parameters_order' => [],`	`'version' => 26`
`'category' => 'TOP',`
`'description_pdf' => undef,`
`'module' => 'TOP'`
`}`
`},`	`},`
`'instance_order' => [`	`'noc_param' => {},`
`'TOP'`	`'compile_assign_type' => {`
`]`	`'TOP_source_reset_in' => 'Direct',`
`}, 'soc' ),`	`'cpu_cpu_en' => 'Direct',`
`'REDEFINE_TOP' => 0`	`'jtag_debug_reset_in' => 'Direct',`
	`'TOP_source_clk_in' => 'Direct',`
	`'smartflit_chanel_t' => 'Direct',`
	`'ni_current_e_addr' => 'Direct',`
	`'ni_current_r_addr' => 'Direct'`
`},`	`},`
`'current_module_param' => undef,`	`'clk_source0' => {`
`'wishbone_bus0' => {`
`'version' => 1`	`'version' => 1`
`},`	`},`
	`'ROM0' => {`
	`'end' => 49152,`
	`'start' => 0`
	`},`
`'instance_order' => [`	`'instance_order' => [`
`'clk_source0',`	`'clk_source0',`
`'wishbone_bus0',`	`'wishbone_bus0',`
`'mor1kx0',`	`'mor1kx0',`
`'single_port_ram0',`	`'single_port_ram0',`
`'ni_master0',`	`'ni_master0',`
`'timer0',`	`'timer0',`
`'ProNoC_jtag_uart0'`	`'ProNoC_jtag_uart0'`
`],`	`],`
	`'hdl_files_ticked' => undef,`
	`'wishbone_bus0' => {`
	`'version' => 1`
	`},`
`'instances' => {`	`'instances' => {`
`'timer0' => {`	`'wishbone_bus0' => {`
`'sockets' => {},`
`'parameters' => {`	`'parameters' => {`
`'Aw' => {`	`'BTEw' => {`
`'value' => '3'`	`'value' => '2 '`
`},`	`},`
`'CNTw' => {`	`'S' => {`
`'value' => '32 '`	`'value' => '4'`
	`},`
	`'SELw' => {`
	`'value' => 'Dw/8'`
`},`	`},`
`'TAGw' => {`	`'TAGw' => {`
`'value' => '3'`	`'value' => '3'`
`},`	`},`
`'Dw' => {`	`'M' => {`
`'value' => '32'`
`},`
`'SELw' => {`
`'value' => '4'`	`'value' => '4'`
`},`	`},`
`'PRESCALER_WIDTH' => {`	`'CTIw' => {`
`'value' => '8'`	`'value' => '3'`
`}`
`},`	`},`
`'parameters_order' => [`	`'Aw' => {`
`'CNTw',`	`'value' => '32'`
`'Dw',`
`'Aw',`
`'TAGw',`
`'SELw',`
`'PRESCALER_WIDTH'`
`],`
`'module' => 'timer',`
`'category' => 'Timer',`
`'parameters_type' => {`
`'Dw' => {},`
`'TAGw' => {},`
`'CNTw' => {},`
`'Aw' => {},`
`'PRESCALER_WIDTH' => {`
`'value' => 'Localparam'`
`},`	`},`
`'SELw' => {}`	`'Dw' => {`
	`'value' => '32'`
	`}`
	`},`
	`'sockets' => {`
	`'snoop' => {`
	`'connection_num' => 'single connection',`
	`'nums' => {`
	`'0' => {`
	`'name' => 'snoop'`
	`}`
`},`	`},`
`'description_pdf' => '/mpsoc/rtl/src_peripheral/timer/timer.pdf',`
`'module_name' => 'timer',`
`'plugs' => {`
`'clk' => {`
`'type' => 'num',`	`'type' => 'num',`
	`'value' => 1`
	`},`
	`'wb_master' => {`
	`'type' => 'param',`
	`'value' => 'M',`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_id' => 'clk_source0',`	`'name' => 'wb_master'`
`'name' => 'clk',`
`'connect_socket' => 'clk',`
`'connect_socket_num' => '0'`
`}`	`}`
`},`	`},`
`'value' => 1,`	`'connection_num' => 'single connection'`
`'connection_num' => undef`
`},`	`},`
`'interrupt_peripheral' => {`	`'wb_addr_map' => {`
`'value' => 1,`
`'type' => 'num',`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_id' => 'mor1kx0',`	`'name' => 'wb_addr_map'`
`'name' => 'intrp',`
`'connect_socket_num' => '1',`
`'connect_socket' => 'interrupt_peripheral'`
`}`	`}`
`},`	`},`
`'connection_num' => undef`	`'connection_num' => 'single connection',`
	`'type' => 'num',`
	`'value' => 1`
`},`	`},`
`'wb_slave' => {`	`'wb_slave' => {`
`'connection_num' => undef,`
`'value' => 1,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'end' => 2516582431,`	`'name' => 'wb_slave'`
`'connect_socket' => 'wb_slave',`
`'base' => 2516582400,`
`'connect_socket_num' => '2',`
`'connect_id' => 'wishbone_bus0',`
`'width' => 5,`
`'name' => 'wb',`
`'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl'`
`}`	`}`
`},`	`},`
`'type' => 'num'`	`'connection_num' => 'single connection',`
	`'value' => 'S',`
	`'type' => 'param'`
	`}`
	`},`
	`'parameters_type' => {`
	`'BTEw' => {},`
	`'S' => {`
	`'value' => 'Localparam'`
	`},`
	`'SELw' => {},`
	`'TAGw' => {},`
	`'M' => {`
	`'value' => 'Localparam'`
	`},`
	`'CTIw' => {},`
	`'Aw' => {`
	`'value' => 'Localparam'`
	`},`
	`'Dw' => {`
	`'value' => 'Localparam'`
	`}`
`},`	`},`
	`'category' => 'Bus',`
	`'module_name' => 'wishbone_bus',`
	`'plugs' => {`
`'reset' => {`	`'reset' => {`
`'connection_num' => undef,`	`'connection_num' => undef,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_socket_num' => '0',`	`'connect_socket_num' => '0',`
`'connect_socket' => 'reset',`
`'connect_id' => 'clk_source0',`	`'connect_id' => 'clk_source0',`
	`'connect_socket' => 'reset',`
`'name' => 'reset'`	`'name' => 'reset'`
`}`	`}`
`},`	`},`
`'type' => 'num',`	`'value' => 1,`
`'value' => 1`	`'type' => 'num'`
`}`
`},`
`'instance_name' => 'timer'`
`},`	`},`
`'ProNoC_jtag_uart0' => {`	`'clk' => {`
`'sockets' => {`
`'jtag_to_wb' => {`
`'connection_num' => 'single connection',`
`'value' => 1,`	`'value' => 1,`
	`'type' => 'num',`
	`'connection_num' => undef,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'name' => 'jtag_to_wb'`	`'connect_socket' => 'clk',`
	`'name' => 'clk',`
	`'connect_socket_num' => '0',`
	`'connect_id' => 'clk_source0'`
	`}`
	`}`
`}`	`}`
`},`	`},`
`'type' => 'num'`	`'description_pdf' => undef,`
	`'instance_name' => 'bus',`
	`'parameters_order' => [`
	`'M',`
	`'S',`
	`'Dw',`
	`'Aw',`
	`'SELw',`
	`'TAGw',`
	`'CTIw',`
	`'BTEw'`
	`],`
	`'module' => 'wishbone_bus'`
`},`	`},`
`'RxD_sim' => {`	`'timer0' => {`
`'connection_num' => 'single connection',`	`'category' => 'Timer',`
`'value' => 1,`	`'module_name' => 'timer',`
	`'description_pdf' => '/mpsoc/rtl/src_peripheral/timer/timer.pdf',`
	`'plugs' => {`
	`'wb_slave' => {`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'name' => 'RxD_sim'`	`'width' => 5,`
	`'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl',`
	`'base' => 2516582400,`
	`'end' => 2516582431,`
	`'connect_socket' => 'wb_slave',`
	`'name' => 'wb',`
	`'connect_socket_num' => '2',`
	`'connect_id' => 'wishbone_bus0'`
`}`	`}`
`},`	`},`
	`'connection_num' => undef,`
	`'value' => 1,`
`'type' => 'num'`	`'type' => 'num'`
`}`
`},`	`},`
`'parameters' => {`	`'reset' => {`
`'SELw' => {`	`'value' => 1,`
`'value' => '4'`	`'type' => 'num',`
	`'nums' => {`
	`'0' => {`
	`'connect_socket_num' => '0',`
	`'connect_id' => 'clk_source0',`
	`'connect_socket' => 'reset',`
	`'name' => 'reset'`
	`}`
`},`	`},`
`'JTAG_CONNECT' => {`	`'connection_num' => undef`
`'value' => '"ALTERA_JTAG_WB"'`
`},`	`},`
`'JSTATUSw' => {`	`'interrupt_peripheral' => {`
`'value' => '8'`	`'nums' => {`
	`'0' => {`
	`'name' => 'intrp',`
	`'connect_socket' => 'interrupt_peripheral',`
	`'connect_id' => 'mor1kx0',`
	`'connect_socket_num' => '1'`
	`}`
`},`	`},`
`'BUFF_Aw' => {`	`'connection_num' => undef,`
`'value' => '4'`	`'type' => 'num',`
	`'value' => 1`
`},`	`},`
`'J2WBw' => {`	`'clk' => {`
`'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1'`	`'value' => 1,`
	`'type' => 'num',`
	`'nums' => {`
	`'0' => {`
	`'name' => 'clk',`
	`'connect_socket' => 'clk',`
	`'connect_id' => 'clk_source0',`
	`'connect_socket_num' => '0'`
	`}`
`},`	`},`
`'JDw' => {`	`'connection_num' => undef`
`'value' => '32'`	`}`
`},`	`},`
`'Dw' => {`	`'parameters_order' => [`
`'value' => '32'`	`'CNTw',`
	`'Dw',`
	`'Aw',`
	`'TAGw',`
	`'SELw',`
	`'PRESCALER_WIDTH'`
	`],`
	`'instance_name' => 'timer',`
	`'module' => 'timer',`
	`'parameters' => {`
	`'PRESCALER_WIDTH' => {`
	`'value' => '8'`
`},`	`},`
`'TAGw' => {`	`'TAGw' => {`
`'value' => '3'`	`'value' => '3'`
`},`	`},`
`'INCLUDE_SIM_PRINTF' => {`	`'Dw' => {`
`'value' => 'SIMPLE_PRINTF'`	`'value' => '32'`
`},`	`},`
`'JAw' => {`	`'CNTw' => {`
`'value' => '32'`	`'value' => '32'`
`},`	`},`
`'WB2Jw' => {`	`'SELw' => {`
`'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'`	`'value' => '4'`
`},`	`},`
`'JTAG_CHAIN' => {`	`'Aw' => {`
`'value' => '3'`	`'value' => '3'`
	`}`
`},`	`},`
`'Aw' => {`	`'parameters_type' => {`
`'value' => '1'`	`'SELw' => {},`
	`'PRESCALER_WIDTH' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'JINDEXw' => {`	`'TAGw' => {},`
`'value' => '8'`	`'Aw' => {},`
	`'CNTw' => {},`
	`'Dw' => {}`
`},`	`},`
`'JTAG_INDEX' => {`	`'sockets' => {}`
`'value' => '126-CORE_ID'`
`}`
`},`	`},`
	`'ni_master0' => {`
	`'module' => 'ni_master',`
	`'instance_name' => 'ni',`
`'parameters_order' => [`	`'parameters_order' => [`
`'Aw',`	`'MAX_TRANSACTION_WIDTH',`
`'SELw',`	`'MAX_BURST_SIZE',`
`'TAGw',`
`'Dw',`	`'Dw',`
`'BUFF_Aw',`	`'S_Aw',`
`'JTAG_INDEX',`	`'M_Aw',`
`'JDw',`	`'TAGw',`
`'JAw',`	`'SELw',`
`'JINDEXw',`	`'CRC_EN',`
`'JSTATUSw',`	`'RAw',`
`'JTAG_CHAIN',`	`'EAw',`
`'JTAG_CONNECT',`	`'HDATA_PRECAPw'`
`'J2WBw',`
`'WB2Jw',`
`'INCLUDE_SIM_PRINTF'`
`],`	`],`
`'module_name' => 'pronoc_jtag_uart',`
`'plugs' => {`	`'plugs' => {`
`'clk' => {`	`'wb_master' => {`
	`'type' => 'num',`
	`'value' => 2,`
	`'connection_num' => undef,`
	`'nums' => {`
	`'0' => {`
	`'connect_socket_num' => '2',`
	`'connect_id' => 'wishbone_bus0',`
	`'connect_socket' => 'wb_master',`
	`'name' => 'wb_send'`
	`},`
	`'1' => {`
	`'connect_socket' => 'wb_master',`
	`'name' => 'wb_receive',`
	`'connect_socket_num' => '3',`
	`'connect_id' => 'wishbone_bus0'`
	`}`
	`}`
	`},`
	`'reset' => {`
`'connection_num' => undef,`	`'connection_num' => undef,`
`'value' => 1,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_id' => 'clk_source0',`	`'connect_id' => 'clk_source0',`
`'name' => 'clk',`
`'connect_socket_num' => '0',`	`'connect_socket_num' => '0',`
`'connect_socket' => 'clk'`	`'name' => 'reset',`
	`'connect_socket' => 'reset'`
`}`	`}`
`},`	`},`
	`'value' => 1,`
`'type' => 'num'`	`'type' => 'num'`
`},`	`},`
	`'interrupt_peripheral' => {`
	`'type' => 'num',`
	`'value' => 1,`
	`'connection_num' => undef,`
	`'nums' => {`
	`'0' => {`
	`'connect_socket' => 'interrupt_peripheral',`
	`'name' => 'interrupt',`
	`'connect_socket_num' => '0',`
	`'connect_id' => 'mor1kx0'`
	`}`
	`}`
	`},`
`'wb_slave' => {`	`'wb_slave' => {`
	`'connection_num' => undef,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'width' => 4,`	`'addr' => '0xb800_0000 0xbfff_ffff custom devices',`
	`'width' => 10,`
	`'connect_id' => 'wishbone_bus0',`
	`'connect_socket_num' => '1',`
`'name' => 'wb_slave',`	`'name' => 'wb_slave',`
`'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',`
`'connect_socket' => 'wb_slave',`	`'connect_socket' => 'wb_slave',`
`'end' => 2415919119,`	`'end' => 3087008767,`
`'base' => 2415919104,`	`'base' => 3087007744`
`'connect_socket_num' => '3',`
`'connect_id' => 'wishbone_bus0'`
`}`	`}`
`},`	`},`
`'type' => 'num',`
`'value' => 1,`	`'value' => 1,`
`'connection_num' => undef`	`'type' => 'num'`
`},`	`},`
`'reset' => {`	`'clk' => {`
`'connection_num' => undef,`
`'value' => 1,`	`'value' => 1,`
`'type' => 'num',`	`'type' => 'num',`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_socket' => 'reset',`	`'name' => 'clk',`
`'connect_socket_num' => '0',`	`'connect_socket' => 'clk',`
`'name' => 'reset',`	`'connect_id' => 'clk_source0',`
`'connect_id' => 'clk_source0'`	`'connect_socket_num' => '0'`
	`}`
	`},`
	`'connection_num' => undef`
	`}`
	`},`
	`'description_pdf' => '/mpsoc/rtl/src_peripheral/ni/NI.pdf',`
	`'module_name' => 'ni_master',`
	`'category' => 'NoC',`
	`'sockets' => {`
	`'ni' => {`
	`'type' => 'num',`
	`'value' => 1,`
	`'connection_num' => 'single connection',`
	`'nums' => {`
	`'0' => {`
	`'name' => 'ni'`
`}`	`}`
`}`	`}`
`}`	`}`
`},`	`},`
`'instance_name' => 'uart',`
`'module' => 'ProNoC_jtag_uart',`
`'parameters_type' => {`	`'parameters_type' => {`
`'SELw' => {},`	`'RAw' => {},`
`'BUFF_Aw' => {`	`'DEBUG_EN' => {`
`'value' => 'Localparam'`	`'value' => 'Parameter'`
`},`	`},`
`'JSTATUSw' => {},`	`'HDATA_PRECAPw' => {`
`'J2WBw' => {},`
`'JTAG_CONNECT' => {`
`'value' => 'Localparam'`	`'value' => 'Localparam'`
`},`	`},`
`'Dw' => {},`	`'PCK_TYPE' => {`
`'JDw' => {},`	`'value' => 'Parameter'`
`'TAGw' => {},`
`'WB2Jw' => {},`
`'JAw' => {},`
`'JTAG_CHAIN' => {`
`'value' => 'Localparam'`
`},`	`},`
`'INCLUDE_SIM_PRINTF' => {`	`'CONGESTION_INDEX' => {`
`'value' => 'Localparam'`	`'value' => 'Parameter'`
`},`	`},`
`'Aw' => {},`	`'T3' => {`
`'JTAG_INDEX' => {`	`'value' => 'Parameter'`
`'value' => 'Localparam'`
`},`	`},`
`'JINDEXw' => {}`	`'CRC_EN' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'description_pdf' => undef,`	`'MCAST_ENDP_LIST' => {`
`'category' => 'Communication'`	`'value' => 'Parameter'`
`},`	`},`
`'wishbone_bus0' => {`	`'Dw' => {`
`'parameters_order' => [`	`'value' => 'Localparam'`
`'M',`
`'S',`
`'Dw',`
`'Aw',`
`'SELw',`
`'TAGw',`
`'CTIw',`
`'BTEw'`
`],`
`'sockets' => {`
`'wb_addr_map' => {`
`'connection_num' => 'single connection',`
`'value' => 1,`
`'type' => 'num',`
`'nums' => {`
`'0' => {`
`'name' => 'wb_addr_map'`
`}`
`}`
`},`	`},`
`'wb_master' => {`	`'SELF_LOOP_EN' => {`
`'connection_num' => 'single connection',`	`'value' => 'Parameter'`
`'value' => 'M',`
`'type' => 'param',`
`'nums' => {`
`'0' => {`
`'name' => 'wb_master'`
`}`
`}`
`},`	`},`
`'wb_slave' => {`	`'TOPOLOGY' => {`
`'value' => 'S',`	`'value' => 'Parameter'`
`'type' => 'param',`
`'nums' => {`
`'0' => {`
`'name' => 'wb_slave'`
`}`
`},`	`},`
`'connection_num' => 'single connection'`	`'T2' => {`
	`'value' => 'Parameter'`
`},`	`},`
`'snoop' => {`	`'EAw' => {},`
`'connection_num' => 'single connection',`	`'BYTE_EN' => {`
`'value' => 1,`	`'value' => 'Parameter'`
`'type' => 'num',`	`},`
`'nums' => {`	`'WEIGHTw' => {`
`'0' => {`	`'value' => 'Parameter'`
`'name' => 'snoop'`	`},`
`}`	`'COMBINATION_TYPE' => {`
`}`	`'value' => 'Parameter'`
	`},`
	`'ESCAP_VC_MASK' => {`
	`'value' => 'Parameter'`
	`},`
	`'MAX_BURST_SIZE' => {`
	`'value' => 'Localparam'`
	`},`
	`'FIRST_ARBITER_EXT_P_EN' => {`
	`'value' => 'Parameter'`
	`},`
	`'SMART_MAX' => {`
	`'value' => 'Parameter'`
	`},`
	`'LB' => {`
	`'value' => 'Parameter'`
	`},`
	`'VC_REALLOCATION_TYPE' => {`
	`'value' => 'Parameter'`
	`},`
	`'SSA_EN' => {`
	`'value' => 'Parameter'`
	`},`
	`'ROUTE_NAME' => {`
	`'value' => 'Parameter'`
	`},`
	`'MUX_TYPE' => {`
	`'value' => 'Parameter'`
	`},`
	`'B' => {`
	`'value' => 'Parameter'`
	`},`
	`'MIN_PCK_SIZE' => {`
	`'value' => 'Parameter'`
	`},`
	`'T1' => {`
	`'value' => 'Parameter'`
	`},`
	`'SELw' => {},`
	`'ADD_PIPREG_AFTER_CROSSBAR' => {`
	`'value' => 'Parameter'`
	`},`
	`'CAST_TYPE' => {`
	`'value' => 'Parameter'`
	`},`
	`'SWA_ARBITER_TYPE' => {`
	`'value' => 'Parameter'`
	`},`
	`'TAGw' => {},`
	`'MAX_TRANSACTION_WIDTH' => {`
	`'value' => 'Localparam'`
	`},`
	`'M_Aw' => {},`
	`'V' => {`
	`'value' => 'Parameter'`
	`},`
	`'Fpay' => {`
	`'value' => 'Parameter'`
	`},`
	`'C' => {`
	`'value' => 'Parameter'`
	`},`
	`'S_Aw' => {},`
	`'AVC_ATOMIC_EN' => {`
	`'value' => 'Parameter'`
`}`	`}`
`},`	`},`
`'parameters' => {`	`'parameters' => {`
`'CTIw' => {`	`'EAw' => {`
`'value' => '3'`	`'value' => '16'`
`},`	`},`
`'Aw' => {`	`'T2' => {`
`'value' => '32'`	`'value' => '2'`
`},`	`},`
`'M' => {`	`'TOPOLOGY' => {`
	`'value' => '"MESH"'`
	`},`
	`'SELF_LOOP_EN' => {`
	`'value' => '"NO"'`
	`},`
	`'COMBINATION_TYPE' => {`
	`'value' => '"COMB_NONSPEC"'`
	`},`
	`'WEIGHTw' => {`
`'value' => ' 4'`	`'value' => ' 4'`
`},`	`},`
`'SELw' => {`	`'BYTE_EN' => {`
`'value' => 'Dw/8'`	`'value' => '1'`
`},`	`},`
`'BTEw' => {`	`'SMART_MAX' => {`
	`'value' => '0'`
	`},`
	`'FIRST_ARBITER_EXT_P_EN' => {`
	`'value' => 1`
	`},`
	`'MAX_BURST_SIZE' => {`
	`'value' => '16'`
	`},`
	`'ESCAP_VC_MASK' => {`
	`'value' => '2\'b01'`
	`},`
	`'PCK_TYPE' => {`
	`'value' => '"MULTI_FLIT"'`
	`},`
	`'HDATA_PRECAPw' => {`
	`'value' => '0'`
	`},`
	`'DEBUG_EN' => {`
	`'value' => '0'`
	`},`
	`'RAw' => {`
	`'value' => '16'`
	`},`
	`'CONGESTION_INDEX' => {`
	`'value' => 3`
	`},`
	`'T3' => {`
	`'value' => '1'`
	`},`
	`'Dw' => {`
	`'value' => '32'`
	`},`
	`'MCAST_ENDP_LIST' => {`
	`'value' => '\'hf'`
	`},`
	`'CRC_EN' => {`
	`'value' => '"NO"'`
	`},`
	`'ADD_PIPREG_AFTER_CROSSBAR' => {`
	`'value' => '1\'b0'`
	`},`
	`'MIN_PCK_SIZE' => {`
`'value' => '2 '`	`'value' => '2 '`
`},`	`},`
`'S' => {`	`'T1' => {`
	`'value' => '2'`
	`},`
	`'SELw' => {`
`'value' => '4'`	`'value' => '4'`
`},`	`},`
	`'ROUTE_NAME' => {`
	`'value' => '"XY"'`
	`},`
	`'MUX_TYPE' => {`
	`'value' => '"BINARY"'`
	`},`
	`'B' => {`
	`'value' => '4'`
	`},`
	`'MAX_TRANSACTION_WIDTH' => {`
	`'value' => '13'`
	`},`
`'TAGw' => {`	`'TAGw' => {`
`'value' => '3'`	`'value' => '3'`
`},`	`},`
`'Dw' => {`	`'CAST_TYPE' => {`
	`'value' => '"UNICAST"'`
	`},`
	`'SWA_ARBITER_TYPE' => {`
	`'value' => '"RRA"'`
	`},`
	`'C' => {`
	`'value' => 0`
	`},`
	`'Fpay' => {`
`'value' => '32'`	`'value' => '32'`
`}`
`},`	`},`
`'category' => 'Bus',`	`'M_Aw' => {`
`'parameters_type' => {`	`'value' => '32'`
`'Aw' => {`
`'value' => 'Localparam'`
`},`	`},`
`'M' => {`	`'V' => {`
`'value' => 'Localparam'`	`'value' => '2'`
`},`	`},`
`'CTIw' => {},`	`'AVC_ATOMIC_EN' => {`
`'S' => {`	`'value' => 0`
`'value' => 'Localparam'`
`},`	`},`
`'Dw' => {`	`'S_Aw' => {`
`'value' => 'Localparam'`	`'value' => '8'`
`},`	`},`
`'TAGw' => {},`	`'LB' => {`
`'SELw' => {},`	`'value' => '4'`
`'BTEw' => {}`
`},`	`},`
`'description_pdf' => undef,`	`'VC_REALLOCATION_TYPE' => {`
`'module' => 'wishbone_bus',`	`'value' => '"NONATOMIC"'`
`'plugs' => {`	`},`
`'reset' => {`	`'SSA_EN' => {`
`'connection_num' => undef,`	`'value' => '"NO"'`
`'value' => 1,`	`}`
`'nums' => {`
`'0' => {`
`'name' => 'reset',`
`'connect_id' => 'clk_source0',`
`'connect_socket' => 'reset',`
`'connect_socket_num' => '0'`
`}`	`}`
`},`	`},`
`'type' => 'num'`	`'clk_source0' => {`
	`'parameters' => {`
	`'FPGA_VENDOR' => {`
	`'value' => '"ALTERA"'`
	`}`
`},`	`},`
	`'sockets' => {`
`'clk' => {`	`'clk' => {`
`'value' => 1,`	`'value' => 1,`
`'type' => 'num',`	`'type' => 'num',`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_id' => 'clk_source0',`	`'name' => 'clk'`
`'name' => 'clk',`
`'connect_socket' => 'clk',`
`'connect_socket_num' => '0'`
`}`
`},`
`'connection_num' => undef`
`}`	`}`
`},`	`},`
`'module_name' => 'wishbone_bus',`	`'connection_num' => 'multi connection'`
`'instance_name' => 'bus'`
`},`	`},`
`'clk_source0' => {`
`'parameters_order' => [`
`'FPGA_VENDOR'`
`],`
`'sockets' => {`
`'reset' => {`	`'reset' => {`
`'connection_num' => 'multi connection',`
`'nums' => {`
`'0' => {`
`'name' => 'reset'`
`}`
`},`
`'type' => 'num',`
`'value' => 1`
`},`
`'clk' => {`
`'value' => 1,`	`'value' => 1,`
`'type' => 'num',`	`'type' => 'num',`
	`'connection_num' => 'multi connection',`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'name' => 'clk'`	`'name' => 'reset'`
`}`	`}`
`},`
`'connection_num' => 'multi connection'`
`}`	`}`
`},`
`'parameters' => {`
`'FPGA_VENDOR' => {`
`'value' => '"ALTERA"'`
`}`	`}`
`},`	`},`
`'description_pdf' => undef,`
`'category' => 'Source',`
`'parameters_type' => {`	`'parameters_type' => {`
`'FPGA_VENDOR' => {`	`'FPGA_VENDOR' => {`
`'value' => 'Localparam'`	`'value' => 'Localparam'`
`}`	`}`
`},`	`},`
`'module' => 'clk_source',`
`'module_name' => 'clk_source',`
`'plugs' => {`	`'plugs' => {`
`'reset' => {`	`'clk' => {`
	`'value' => 1,`
	`'type' => 'num',`
`'connection_num' => undef,`	`'connection_num' => undef,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_id' => 'IO',`	`'connect_socket' => undef,`
`'name' => 'reset',`	`'name' => 'clk',`
`'connect_socket_num' => undef,`	`'connect_socket_num' => undef,`
`'connect_socket' => undef`	`'connect_id' => 'IO'`
	`}`
`}`	`}`
`},`	`},`
	`'reset' => {`
	`'value' => 1,`
`'type' => 'num',`	`'type' => 'num',`
`'value' => 1`
`},`
`'clk' => {`
`'connection_num' => undef,`	`'connection_num' => undef,`
`'value' => 1,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_socket_num' => undef,`
`'connect_socket' => undef,`	`'connect_socket' => undef,`
`'name' => 'clk',`	`'name' => 'reset',`
	`'connect_socket_num' => undef,`
`'connect_id' => 'IO'`	`'connect_id' => 'IO'`
`}`	`}`
`},`	`}`
`'type' => 'num'`
`}`	`}`
`},`	`},`
`'instance_name' => 'source'`	`'description_pdf' => undef,`
	`'category' => 'Source',`
	`'module_name' => 'clk_source',`
	`'module' => 'clk_source',`
	`'instance_name' => 'source',`
	`'parameters_order' => [`
	`'FPGA_VENDOR'`
	`]`
`},`	`},`
`'ni_master0' => {`	`'single_port_ram0' => {`
`'parameters' => {`	`'parameters' => {`
`'Dw' => {`	`'INIT_FILE_PATH' => {`
`'value' => '32'`	`'value' => 'SW_LOC'`
`},`
`'COMBINATION_TYPE' => {`
`'value' => '"COMB_NONSPEC"'`
`},`
`'SWA_ARBITER_TYPE' => {`
`'value' => '"RRA"'`
`},`
`'WEIGHTw' => {`
`'value' => '4'`
`},`
`'CONGESTION_INDEX' => {`
`'value' => 3`
`},`
`'MAX_TRANSACTION_WIDTH' => {`
`'value' => '13'`
`},`	`},`
`'PCK_TYPE' => {`	`'CTIw' => {`
`'value' => '"MULTI_FLIT"'`	`'value' => '3'`
`},`	`},`
`'FIRST_ARBITER_EXT_P_EN' => {`	`'Dw' => {`
`'value' => 1`	`'value' => '32'`
`},`	`},`
`'SELF_LOOP_EN' => {`	`'WB_Byte_Aw' => {`
`'value' => '"NO"'`	`'value' => 'WB_Aw+2'`
`},`	`},`
`'CRC_EN' => {`	`'FPGA_VENDOR' => {`
`'value' => '"NO"'`	`'value' => '"ALTERA"'`
`},`	`},`
`'EAw' => {`	`'JDw' => {`
`'value' => '16'`	`'value' => 'Dw'`
`},`	`},`
`'B' => {`	`'BURST_MODE' => {`
`'value' => '4'`	`'value' => '"ENABLED"'`
`},`	`},`
`'TOPOLOGY' => {`	`'WB_Aw' => {`
`'value' => '"MESH"'`	`'value' => '20'`
`},`	`},`
`'V' => {`	`'JINDEXw' => {`
`'value' => '2'`	`'value' => '8'`
`},`	`},`
`'C' => {`	`'MEM_CONTENT_FILE_NAME' => {`
`'value' => 0`	`'value' => '"ram0"'`
`},`	`},`
`'T3' => {`	`'JAw' => {`
`'value' => '1'`	`'value' => '32'`
`},`	`},`
`'VC_REALLOCATION_TYPE' => {`	`'JSTATUSw' => {`
`'value' => '"NONATOMIC"'`	`'value' => '8'`
`},`	`},`
`'ROUTE_NAME' => {`	`'J2WBw' => {`
`'value' => '"XY"'`	`'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1'`
`},`	`},`
`'SMART_MAX' => {`	`'BYTE_WR_EN' => {`
`'value' => '0'`	`'value' => '"YES"'`
`},`	`},`
`'DEBUG_EN' => {`	`'CORE_NUM' => {`
`'value' => '0'`	`'value' => 'CORE_ID'`
`},`	`},`
`'SSA_EN' => {`	`'JTAG_INDEX' => {`
`'value' => '"NO"'`	`'value' => 'CORE_ID'`
`},`	`},`
`'ADD_PIPREG_AFTER_CROSSBAR' => {`	`'JTAG_CHAIN' => {`
`'value' => '1\'b0'`	`'value' => '4'`
`},`	`},`
`'MAX_BURST_SIZE' => {`	`'Aw' => {`
`'value' => '16'`	`'value' => '14'`
`},`	`},`
`'TAGw' => {`	`'TAGw' => {`
`'value' => '3'`	`'value' => '3'`
`},`	`},`
`'AVC_ATOMIC_EN' => {`	`'JTAG_CONNECT' => {`
`'value' => 0`	`'value' => '"ALTERA_JTAG_WB"'`
`},`	`},`
`'MIN_PCK_SIZE' => {`	`'BTEw' => {`
`'value' => '2'`	`'value' => '2'`
`},`	`},`
`'S_Aw' => {`	`'SELw' => {`
`'value' => '8'`	`'value' => 'Dw/8'`
`},`	`},`
`'Fpay' => {`	`'WB2Jw' => {`
`'value' => '32'`	`'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'`
`},`	`},`
`'T1' => {`	`'INITIAL_EN' => {`
`'value' => '2'`	`'value' => '"YES"'`
	`}`
`},`	`},`
`'MUX_TYPE' => {`	`'parameters_type' => {`
`'value' => '"BINARY"'`	`'FPGA_VENDOR' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'SELw' => {`	`'WB_Aw' => {`
`'value' => '4'`	`'value' => 'Localparam'`
`},`	`},`
`'BYTE_EN' => {`	`'JDw' => {},`
`'value' => '1'`	`'BURST_MODE' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'M_Aw' => {`	`'JINDEXw' => {},`
`'value' => '32'`	`'JAw' => {},`
	`'MEM_CONTENT_FILE_NAME' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'LB' => {`	`'CTIw' => {},`
`'value' => '4'`	`'INIT_FILE_PATH' => {},`
	`'WB_Byte_Aw' => {},`
	`'Dw' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'HDATA_PRECAPw' => {`	`'TAGw' => {},`
`'value' => '0'`	`'SELw' => {},`
	`'BTEw' => {},`
	`'JTAG_CONNECT' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'ESCAP_VC_MASK' => {`	`'INITIAL_EN' => {`
`'value' => '2\'b01'`	`'value' => 'Localparam'`
	`},`
	`'WB2Jw' => {},`
	`'JSTATUSw' => {},`
	`'JTAG_INDEX' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'T2' => {`	`'CORE_NUM' => {},`
`'value' => '2'`	`'BYTE_WR_EN' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'RAw' => {`	`'J2WBw' => {},`
`'value' => '16'`	`'Aw' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'CAST_TYPE' => {`	`'JTAG_CHAIN' => {`
`'value' => '"UNICAST"'`	`'value' => 'Localparam'`
`}`	`}`
`},`	`},`
`'sockets' => {`	`'sockets' => {`
`'ni' => {`	`'jtag_to_wb' => {`
`'connection_num' => 'single connection',`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'name' => 'ni'`	`'name' => 'jtag_to_wb'`
`}`	`}`
`},`	`},`
	`'connection_num' => 'single connection',`
`'type' => 'num',`	`'type' => 'num',`
`'value' => 1`	`'value' => 1`
`}`	`}`
`},`	`},`
`'parameters_order' => [`	`'category' => 'RAM',`
`'MAX_TRANSACTION_WIDTH',`	`'module_name' => 'wb_single_port_ram',`
`'MAX_BURST_SIZE',`	`'description_pdf' => '/mpsoc/rtl/src_peripheral/ram/RAM.pdf',`
`'Dw',`
`'S_Aw',`
`'M_Aw',`
`'TAGw',`
`'SELw',`
`'CRC_EN',`
`'RAw',`
`'EAw',`
`'HDATA_PRECAPw'`
`],`
`'instance_name' => 'ni',`
`'plugs' => {`	`'plugs' => {`
`'reset' => {`	`'clk' => {`
`'connection_num' => undef,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'name' => 'reset',`	`'connect_socket' => 'clk',`
`'connect_id' => 'clk_source0',`	`'name' => 'clk',`
`'connect_socket' => 'reset',`	`'connect_socket_num' => '0',`
`'connect_socket_num' => '0'`	`'connect_id' => 'clk_source0'`
`}`	`}`
`},`	`},`
`'type' => 'num',`
`'value' => 1`
`},`
`'wb_master' => {`
`'connection_num' => undef,`	`'connection_num' => undef,`
`'value' => 2,`	`'value' => 1,`
`'type' => 'num',`	`'type' => 'num'`
`'nums' => {`
`'0' => {`
`'name' => 'wb_send',`
`'connect_id' => 'wishbone_bus0',`
`'connect_socket_num' => '2',`
`'connect_socket' => 'wb_master'`
`},`
`'1' => {`
`'name' => 'wb_receive',`
`'connect_id' => 'wishbone_bus0',`
`'connect_socket' => 'wb_master',`
`'connect_socket_num' => '3'`
`}`
`}`
`},`	`},`
`'wb_slave' => {`	`'reset' => {`
`'type' => 'num',`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_socket_num' => '1',`	`'connect_socket_num' => '0',`
`'end' => 3087008767,`	`'connect_id' => 'clk_source0',`
`'connect_socket' => 'wb_slave',`	`'connect_socket' => 'reset',`
`'base' => 3087007744,`	`'name' => 'reset'`
`'connect_id' => 'wishbone_bus0',`
`'width' => 10,`
`'addr' => '0xb800_0000 0xbfff_ffff custom devices',`
`'name' => 'wb_slave'`
`}`	`}`
`},`	`},`
	`'connection_num' => undef,`
`'value' => 1,`	`'value' => 1,`
`'connection_num' => undef`	`'type' => 'num'`
`},`	`},`
`'interrupt_peripheral' => {`	`'wb_slave' => {`
`'connection_num' => undef,`	`'connection_num' => undef,`
`'type' => 'num',`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'name' => 'interrupt',`	`'addr' => '0x0000_0000 0x3fff_ffff RAM',`
`'connect_id' => 'mor1kx0',`	`'width' => 'WB_Byte_Aw',`
`'connect_socket_num' => '0',`	`'connect_socket_num' => '0',`
`'connect_socket' => 'interrupt_peripheral'`	`'connect_id' => 'wishbone_bus0',`
	`'connect_socket' => 'wb_slave',`
	`'end' => 4194303,`
	`'base' => 0,`
	`'name' => 'wb'`
`}`	`}`
`},`	`},`
`'value' => 1`
`},`
`'clk' => {`
`'value' => 1,`	`'value' => 1,`
`'nums' => {`	`'type' => 'num'`
`'0' => {`
`'connect_socket_num' => '0',`
`'connect_socket' => 'clk',`
`'name' => 'clk',`
`'connect_id' => 'clk_source0'`
`}`	`}`
`},`	`},`
`'type' => 'num',`	`'parameters_order' => [`
`'connection_num' => undef`	`'Dw',`
`}`	`'Aw',`
	`'WB_Aw',`
	`'BYTE_WR_EN',`
	`'FPGA_VENDOR',`
	`'JTAG_CONNECT',`
	`'JTAG_INDEX',`
	`'CORE_NUM',`
	`'TAGw',`
	`'SELw',`
	`'CTIw',`
	`'BTEw',`
	`'WB_Byte_Aw',`
	`'BURST_MODE',`
	`'MEM_CONTENT_FILE_NAME',`
	`'INITIAL_EN',`
	`'INIT_FILE_PATH',`
	`'JDw',`
	`'JAw',`
	`'JSTATUSw',`
	`'JINDEXw',`
	`'J2WBw',`
	`'WB2Jw',`
	`'JTAG_CHAIN'`
	`],`
	`'instance_name' => 'ram',`
	`'module' => 'single_port_ram'`
`},`	`},`
`'module_name' => 'ni_master',`	`'mor1kx0' => {`
`'module' => 'ni_master',`
`'description_pdf' => '/mpsoc/rtl/src_peripheral/ni/NI.pdf',`
`'parameters_type' => {`	`'parameters_type' => {`
`'EAw' => {},`	`'FEATURE_INSTRUCTIONCACHE' => {`
`'B' => {`
`'value' => 'Parameter'`
`},`
`'TOPOLOGY' => {`
`'value' => 'Parameter'`
`},`
`'MAX_TRANSACTION_WIDTH' => {`
`'value' => 'Localparam'`	`'value' => 'Localparam'`
`},`	`},`
`'PCK_TYPE' => {`	`'OPTION_SHIFTER' => {`
`'value' => 'Parameter'`
`},`
`'SELF_LOOP_EN' => {`
`'value' => 'Parameter'`
`},`
`'FIRST_ARBITER_EXT_P_EN' => {`
`'value' => 'Parameter'`
`},`
`'CRC_EN' => {`
`'value' => 'Localparam'`	`'value' => 'Localparam'`
`},`	`},`
`'SWA_ARBITER_TYPE' => {`	`'FEATURE_IMMU' => {`
`'value' => 'Parameter'`
`},`
`'WEIGHTw' => {`
`'value' => 'Parameter'`
`},`
`'CONGESTION_INDEX' => {`
`'value' => 'Parameter'`
`},`
`'Dw' => {`
`'value' => 'Localparam'`	`'value' => 'Localparam'`
`},`	`},`
`'COMBINATION_TYPE' => {`	`'IRQ_NUM' => {},`
`'value' => 'Parameter'`	`'FEATURE_DMMU' => {`
`},`
`'LB' => {`
`'value' => 'Parameter'`
`},`
`'M_Aw' => {},`
`'HDATA_PRECAPw' => {`
`'value' => 'Localparam'`	`'value' => 'Localparam'`
`},`	`},`
`'T2' => {`	`'FEATURE_DIVIDER' => {`
`'value' => 'Parameter'`
`},`
`'ESCAP_VC_MASK' => {`
`'value' => 'Parameter'`
`},`
`'RAw' => {},`
`'CAST_TYPE' => {`
`'value' => 'Parameter'`
`},`
`'AVC_ATOMIC_EN' => {`
`'value' => 'Parameter'`
`},`
`'TAGw' => {},`
`'MIN_PCK_SIZE' => {`
`'value' => 'Parameter'`
`},`
`'S_Aw' => {},`
`'MUX_TYPE' => {`
`'value' => 'Parameter'`
`},`
`'Fpay' => {`
`'value' => 'Parameter'`
`},`
`'T1' => {`
`'value' => 'Parameter'`
`},`
`'SELw' => {},`
`'BYTE_EN' => {`
`'value' => 'Parameter'`
`},`
`'SMART_MAX' => {`
`'value' => 'Parameter'`
`},`
`'DEBUG_EN' => {`
`'value' => 'Parameter'`
`},`
`'SSA_EN' => {`
`'value' => 'Parameter'`
`},`
`'ADD_PIPREG_AFTER_CROSSBAR' => {`
`'value' => 'Parameter'`
`},`
`'MAX_BURST_SIZE' => {`
`'value' => 'Localparam'`	`'value' => 'Localparam'`
`},`	`},`
`'V' => {`	`'OPTION_DCACHE_SNOOP' => {`
`'value' => 'Parameter'`	`'value' => 'Localparam'`
`},`
`'C' => {`
`'value' => 'Parameter'`
`},`
`'T3' => {`
`'value' => 'Parameter'`
`},`	`},`
`'VC_REALLOCATION_TYPE' => {`	`'OPTION_OPERAND_WIDTH' => {},`
`'value' => 'Parameter'`	`'FEATURE_DATACACHE' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'ROUTE_NAME' => {`	`'FEATURE_MULTIPLIER' => {`
`'value' => 'Parameter'`	`'value' => 'Localparam'`
`}`	`}`
`},`	`},`
`'category' => 'NoC'`	`'sockets' => {`
	`'interrupt_peripheral' => {`
	`'nums' => {`
	`'0' => {`
	`'name' => 'interrupt_peripheral'`
	`}`
`},`	`},`
`'mor1kx0' => {`	`'connection_num' => 'single connection',`
`'description_pdf' => undef,`	`'value' => 'IRQ_NUM',`
`'parameters_type' => {`	`'type' => 'param'`
`'FEATURE_MULTIPLIER' => {`	`}`
`'value' => 'Localparam'`
`},`	`},`
`'OPTION_DCACHE_SNOOP' => {`	`'parameters' => {`
`'value' => 'Localparam'`	`'FEATURE_INSTRUCTIONCACHE' => {`
	`'value' => '"ENABLED"'`
`},`	`},`
`'FEATURE_DMMU' => {`	`'IRQ_NUM' => {`
`'value' => 'Localparam'`	`'value' => '32'`
`},`	`},`
`'FEATURE_IMMU' => {`	`'FEATURE_IMMU' => {`
`'value' => 'Localparam'`	`'value' => '"ENABLED"'`
	`},`
	`'OPTION_SHIFTER' => {`
	`'value' => '"BARREL"'`
`},`	`},`
`'IRQ_NUM' => {},`
`'FEATURE_DIVIDER' => {`	`'FEATURE_DIVIDER' => {`
`'value' => 'Localparam'`	`'value' => '"SERIAL"'`
`},`	`},`
`'OPTION_SHIFTER' => {`	`'FEATURE_DMMU' => {`
`'value' => 'Localparam'`	`'value' => '"ENABLED"'`
	`},`
	`'OPTION_DCACHE_SNOOP' => {`
	`'value' => '"ENABLED"'`
`},`	`},`
`'OPTION_OPERAND_WIDTH' => {},`
`'FEATURE_DATACACHE' => {`	`'FEATURE_DATACACHE' => {`
`'value' => 'Localparam'`	`'value' => '"ENABLED"'`
`},`	`},`
`'FEATURE_INSTRUCTIONCACHE' => {`	`'OPTION_OPERAND_WIDTH' => {`
`'value' => 'Localparam'`	`'value' => '32'`
	`},`
	`'FEATURE_MULTIPLIER' => {`
	`'value' => '"THREESTAGE"'`
`}`	`}`
`},`	`},`
`'category' => 'Processor',`
`'module' => 'mor1kx',`	`'module' => 'mor1kx',`
	`'parameters_order' => [`
	`'OPTION_OPERAND_WIDTH',`
	`'IRQ_NUM',`
	`'OPTION_DCACHE_SNOOP',`
	`'FEATURE_INSTRUCTIONCACHE',`
	`'FEATURE_DATACACHE',`
	`'FEATURE_IMMU',`
	`'FEATURE_DMMU',`
	`'FEATURE_MULTIPLIER',`
	`'FEATURE_DIVIDER',`
	`'OPTION_SHIFTER'`
	`],`
`'instance_name' => 'cpu',`	`'instance_name' => 'cpu',`
	`'description_pdf' => undef,`
`'plugs' => {`	`'plugs' => {`
`'wb_master' => {`
`'value' => 2,`
`'nums' => {`
`'1' => {`
`'connect_socket_num' => '1',`
`'connect_socket' => 'wb_master',`
`'name' => 'dwb',`
`'connect_id' => 'wishbone_bus0'`
`},`
`'0' => {`
`'connect_socket' => 'wb_master',`
`'connect_socket_num' => '0',`
`'name' => 'iwb',`
`'connect_id' => 'wishbone_bus0'`
`}`
`},`
`'type' => 'num',`
`'connection_num' => undef`
`},`
`'clk' => {`	`'clk' => {`
`'connection_num' => undef,`	`'connection_num' => undef,`
`'value' => 1,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_socket' => 'clk',`	`'connect_socket' => 'clk',`
	`'name' => 'clk',`
`'connect_socket_num' => '0',`	`'connect_socket_num' => '0',`
`'connect_id' => 'clk_source0',`	`'connect_id' => 'clk_source0'`
`'name' => 'clk'`
`}`	`}`
`},`	`},`
	`'value' => 1,`
`'type' => 'num'`	`'type' => 'num'`
`},`	`},`
`'snoop' => {`	`'snoop' => {`
	`'value' => 1,`
	`'type' => 'num',`
	`'connection_num' => undef,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_socket' => 'snoop',`
`'connect_socket_num' => '0',`
`'connect_id' => 'wishbone_bus0',`	`'connect_id' => 'wishbone_bus0',`
`'name' => 'snoop'`	`'connect_socket_num' => '0',`
	`'name' => 'snoop',`
	`'connect_socket' => 'snoop'`
	`}`
`}`	`}`
`},`	`},`
`'type' => 'num',`	`'enable' => {`
	`'nums' => {`
	`'0' => {`
	`'connect_id' => 'IO',`
	`'connect_socket_num' => undef,`
	`'name' => 'enable',`
	`'connect_socket' => undef`
	`}`
	`},`
	`'connection_num' => undef,`
`'value' => 1,`	`'value' => 1,`
`'connection_num' => undef`	`'type' => 'num'`
`},`	`},`
`'reset' => {`	`'reset' => {`
`'connection_num' => undef,`
`'value' => 1,`	`'value' => 1,`
`'type' => 'num',`	`'type' => 'num',`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
	`'connect_socket' => 'reset',`
`'name' => 'reset',`	`'name' => 'reset',`
`'connect_id' => 'clk_source0',`
`'connect_socket_num' => '0',`	`'connect_socket_num' => '0',`
`'connect_socket' => 'reset'`	`'connect_id' => 'clk_source0'`
`}`
`}`	`}`
`},`	`},`
`'enable' => {`	`'connection_num' => undef`
	`},`
	`'wb_master' => {`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'name' => 'enable',`	`'connect_id' => 'wishbone_bus0',`
`'connect_id' => 'IO',`	`'connect_socket_num' => '0',`
`'connect_socket' => undef,`	`'name' => 'iwb',`
`'connect_socket_num' => undef`	`'connect_socket' => 'wb_master'`
	`},`
	`'1' => {`
	`'connect_socket' => 'wb_master',`
	`'name' => 'dwb',`
	`'connect_socket_num' => '1',`
	`'connect_id' => 'wishbone_bus0'`
`}`	`}`
`},`	`},`
	`'connection_num' => undef,`
`'type' => 'num',`	`'type' => 'num',`
`'value' => 1,`	`'value' => 2`
`'connection_num' => undef`
`}`	`}`
`},`	`},`
`'module_name' => 'mor1k',`	`'category' => 'Processor',`
`'parameters_order' => [`	`'module_name' => 'mor1k'`
`'OPTION_OPERAND_WIDTH',`	`},`
`'IRQ_NUM',`	`'ProNoC_jtag_uart0' => {`
`'OPTION_DCACHE_SNOOP',`
`'FEATURE_INSTRUCTIONCACHE',`
`'FEATURE_DATACACHE',`
`'FEATURE_IMMU',`
`'FEATURE_DMMU',`
`'FEATURE_MULTIPLIER',`
`'FEATURE_DIVIDER',`
`'OPTION_SHIFTER'`
`],`
`'parameters' => {`	`'parameters' => {`
`'FEATURE_INSTRUCTIONCACHE' => {`	`'Dw' => {`
`'value' => '"ENABLED"'`	`'value' => '32'`
`},`	`},`
`'FEATURE_DATACACHE' => {`	`'JTAG_INDEX' => {`
`'value' => '"ENABLED"'`	`'value' => '126-CORE_ID'`
`},`	`},`
`'OPTION_SHIFTER' => {`	`'J2WBw' => {`
`'value' => '"BARREL"'`	`'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1'`
`},`	`},`
`'OPTION_OPERAND_WIDTH' => {`	`'Aw' => {`
`'value' => '32'`	`'value' => '1'`
`},`	`},`
`'FEATURE_DIVIDER' => {`	`'INCLUDE_SIM_PRINTF' => {`
`'value' => '"SERIAL"'`	`'value' => 'SIMPLE_PRINTF'`
`},`	`},`
`'IRQ_NUM' => {`	`'JTAG_CHAIN' => {`
	`'value' => '3'`
	`},`
	`'JSTATUSw' => {`
	`'value' => '8'`
	`},`
	`'JINDEXw' => {`
	`'value' => '8'`
	`},`
	`'JAw' => {`
`'value' => '32'`	`'value' => '32'`
`},`	`},`
`'FEATURE_IMMU' => {`	`'WB2Jw' => {`
`'value' => '"ENABLED"'`	`'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'`
`},`	`},`
`'OPTION_DCACHE_SNOOP' => {`	`'TAGw' => {`
`'value' => '"ENABLED"'`	`'value' => '3'`
`},`	`},`
`'FEATURE_DMMU' => {`	`'SELw' => {`
`'value' => '"ENABLED"'`	`'value' => '4'`
`},`	`},`
`'FEATURE_MULTIPLIER' => {`	`'BUFF_Aw' => {`
`'value' => '"THREESTAGE"'`	`'value' => '4'`
`}`
`},`	`},`
`'sockets' => {`	`'JTAG_CONNECT' => {`
`'interrupt_peripheral' => {`	`'value' => '"ALTERA_JTAG_WB"'`
`'connection_num' => 'single connection',`
`'value' => 'IRQ_NUM',`
`'nums' => {`
`'0' => {`
`'name' => 'interrupt_peripheral'`
`}`
`},`	`},`
`'type' => 'param'`	`'JDw' => {`
`}`	`'value' => '32'`
`}`	`}`
`},`	`},`
`'single_port_ram0' => {`
`'sockets' => {`	`'sockets' => {`
`'jtag_to_wb' => {`	`'jtag_to_wb' => {`
`'connection_num' => 'single connection',`	`'connection_num' => 'single connection',`
`'value' => 1,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'name' => 'jtag_to_wb'`	`'name' => 'jtag_to_wb'`
`}`	`}`
`},`	`},`
	`'value' => 1,`
`'type' => 'num'`	`'type' => 'num'`
`}`
`},`
`'parameters' => {`
`'BURST_MODE' => {`
`'value' => '"ENABLED"'`
`},`
`'Dw' => {`
`'value' => '32'`
`},`
`'INITIAL_EN' => {`
`'value' => '"YES"'`
`},`
`'JSTATUSw' => {`
`'value' => '8'`
`},`
`'JAw' => {`
`'value' => '32'`
`},`
`'CTIw' => {`
`'value' => '3'`
`},`	`},`
`'JTAG_CHAIN' => {`	`'RxD_sim' => {`
`'value' => '4'`	`'nums' => {`
`},`	`'0' => {`
`'INIT_FILE_PATH' => {`	`'name' => 'RxD_sim'`
`'value' => 'SW_LOC'`	`}`
`},`	`},`
`'FPGA_VENDOR' => {`	`'connection_num' => 'single connection',`
`'value' => '"ALTERA"'`	`'value' => 1,`
	`'type' => 'num'`
	`}`
`},`	`},`
	`'parameters_type' => {`
	`'JSTATUSw' => {},`
	`'Dw' => {},`
`'JTAG_INDEX' => {`	`'JTAG_INDEX' => {`
`'value' => 'CORE_ID'`	`'value' => 'Localparam'`
`},`
`'WB_Byte_Aw' => {`
`'value' => 'WB_Aw+2'`
`},`
`'BYTE_WR_EN' => {`
`'value' => '"YES"'`
`},`
`'BTEw' => {`
`'value' => '2'`
`},`
`'SELw' => {`
`'value' => 'Dw/8'`
`},`	`},`
`'TAGw' => {`	`'J2WBw' => {},`
`'value' => '3'`	`'Aw' => {},`
	`'INCLUDE_SIM_PRINTF' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'JDw' => {`	`'JTAG_CHAIN' => {`
`'value' => 'Dw'`	`'value' => 'Localparam'`
`},`	`},`
`'J2WBw' => {`	`'TAGw' => {},`
`'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1'`	`'SELw' => {},`
	`'BUFF_Aw' => {`
	`'value' => 'Localparam'`
`},`	`},`
`'JTAG_CONNECT' => {`	`'JTAG_CONNECT' => {`
`'value' => '"ALTERA_JTAG_WB"'`	`'value' => 'Localparam'`
`},`	`},`
`'CORE_NUM' => {`	`'JDw' => {},`
`'value' => 'CORE_ID'`	`'JINDEXw' => {},`
	`'JAw' => {},`
	`'WB2Jw' => {}`
`},`	`},`
`'WB2Jw' => {`	`'category' => 'Communication',`
`'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'`	`'module_name' => 'pronoc_jtag_uart',`
	`'plugs' => {`
	`'reset' => {`
	`'connection_num' => undef,`
	`'nums' => {`
	`'0' => {`
	`'connect_id' => 'clk_source0',`
	`'connect_socket_num' => '0',`
	`'name' => 'reset',`
	`'connect_socket' => 'reset'`
	`}`
`},`	`},`
`'JINDEXw' => {`	`'value' => 1,`
`'value' => '8'`	`'type' => 'num'`
`},`	`},`
`'MEM_CONTENT_FILE_NAME' => {`	`'wb_slave' => {`
`'value' => '"ram0"'`	`'connection_num' => undef,`
	`'nums' => {`
	`'0' => {`
	`'base' => 2415919104,`
	`'end' => 2415919119,`
	`'connect_socket' => 'wb_slave',`
	`'name' => 'wb_slave',`
	`'connect_socket_num' => '3',`
	`'connect_id' => 'wishbone_bus0',`
	`'width' => 4,`
	`'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller'`
	`}`
`},`	`},`
`'WB_Aw' => {`	`'type' => 'num',`
`'value' => '20'`	`'value' => 1`
`},`	`},`
`'Aw' => {`	`'clk' => {`
`'value' => '14'`	`'nums' => {`
	`'0' => {`
	`'connect_socket' => 'clk',`
	`'name' => 'clk',`
	`'connect_socket_num' => '0',`
	`'connect_id' => 'clk_source0'`
	`}`
	`},`
	`'connection_num' => undef,`
	`'type' => 'num',`
	`'value' => 1`
`}`	`}`
`},`	`},`
	`'description_pdf' => undef,`
	`'instance_name' => 'uart',`
`'parameters_order' => [`	`'parameters_order' => [`
`'Dw',`
`'Aw',`	`'Aw',`
`'WB_Aw',`
`'BYTE_WR_EN',`
`'FPGA_VENDOR',`
`'JTAG_CONNECT',`
`'JTAG_INDEX',`
`'CORE_NUM',`
`'TAGw',`
`'SELw',`	`'SELw',`
`'CTIw',`	`'TAGw',`
`'BTEw',`	`'Dw',`
`'WB_Byte_Aw',`	`'BUFF_Aw',`
`'BURST_MODE',`	`'JTAG_INDEX',`
`'MEM_CONTENT_FILE_NAME',`
`'INITIAL_EN',`
`'INIT_FILE_PATH',`
`'JDw',`	`'JDw',`
`'JAw',`	`'JAw',`
`'JSTATUSw',`
`'JINDEXw',`	`'JINDEXw',`
	`'JSTATUSw',`
	`'JTAG_CHAIN',`
	`'JTAG_CONNECT',`
`'J2WBw',`	`'J2WBw',`
`'WB2Jw',`	`'WB2Jw',`
`'JTAG_CHAIN'`	`'INCLUDE_SIM_PRINTF'`
`],`	`],`
`'module' => 'single_port_ram',`	`'module' => 'ProNoC_jtag_uart'`
`'description_pdf' => '/mpsoc/rtl/src_peripheral/ram/RAM.pdf',`	`}`
`'category' => 'RAM',`
`'parameters_type' => {`
`'JAw' => {},`
`'JTAG_CHAIN' => {`
`'value' => 'Localparam'`
`},`
`'CTIw' => {},`
`'INIT_FILE_PATH' => {},`
`'FPGA_VENDOR' => {`
`'value' => 'Localparam'`
`},`
`'JTAG_INDEX' => {`
`'value' => 'Localparam'`
`},`
`'BURST_MODE' => {`
`'value' => 'Localparam'`
`},`
`'Dw' => {`
`'value' => 'Localparam'`
`},`
`'INITIAL_EN' => {`
`'value' => 'Localparam'`
`},`	`},`
`'JSTATUSw' => {},`	`'compile_pin' => {},`
`'CORE_NUM' => {},`	`'RAM0' => {`
`'WB2Jw' => {},`	`'start' => 49152,`
`'JINDEXw' => {},`	`'end' => 65536`
`'MEM_CONTENT_FILE_NAME' => {`
`'value' => 'Localparam'`
`},`	`},`
`'WB_Aw' => {`	`'MEM0' => {`
`'value' => 'Localparam'`	`'percent' => 75,`
	`'width' => '14'`
`},`	`},`
`'Aw' => {`	`'single_port_ram0' => {`
`'value' => 'Localparam'`	`'version' => 39`
`},`	`},`
`'WB_Byte_Aw' => {},`	`'compile_pin_range_lsb' => {},`
`'BTEw' => {},`	`'compile' => {`
`'BYTE_WR_EN' => {`	`'modelsim_bin' => '/home/alireza/intelFPGA_lite/questa/questasim/bin',`
`'value' => 'Localparam'`	`'board' => 'DE5',`
	`'compilers' => 'QuartusII,Vivado,Verilator,Modelsim',`
	`'type' => 'QuartusII',`
	`'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin'`
`},`	`},`
`'SELw' => {},`	`'gui_status' => {`
`'JDw' => {},`	`'status' => 'ideal',`
`'TAGw' => {},`	`'timeout' => 0`
`'JTAG_CONNECT' => {`
`'value' => 'Localparam'`
`},`	`},`
`'J2WBw' => {}`	`'SOURCE_SET' => {`
	`'clk_0_name' => 'source_clk_in',`
	`'REDEFINE_TOP' => 0,`
	`'SOC' => bless( {`
	`'hdl_files' => undef,`
	`'TOP' => {`
	`'version' => 0`
`},`	`},`
	`'instance_order' => [`
	`'TOP'`
	`],`
	`'instances' => {`
	`'TOP' => {`
`'plugs' => {`	`'plugs' => {`
`'wb_slave' => {`	`'reset' => {`
`'connection_num' => undef,`	`'connection_num' => undef,`
`'value' => 1,`
`'type' => 'num',`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'width' => 'WB_Byte_Aw',`	`'connect_socket' => undef,`
`'name' => 'wb',`	`'name' => 'source_reset_in',`
`'addr' => '0x0000_0000 0x3fff_ffff RAM',`	`'connect_socket_num' => undef,`
`'base' => 0,`	`'connect_id' => 'IO'`
`'end' => 4194303,`
`'connect_socket' => 'wb_slave',`
`'connect_socket_num' => '0',`
`'connect_id' => 'wishbone_bus0'`
`}`
`}`	`}`
`},`	`},`
	`'value' => 1,`
	`'type' => 'num'`
	`},`
`'clk' => {`	`'clk' => {`
	`'connection_num' => undef,`
`'nums' => {`	`'nums' => {`
`'0' => {`	`'0' => {`
`'connect_socket' => 'clk',`	`'connect_id' => 'IO',`
`'connect_socket_num' => '0',`	`'connect_socket_num' => undef,`
`'connect_id' => 'clk_source0',`	`'name' => 'source_clk_in',`
`'name' => 'clk'`	`'connect_socket' => undef`
`}`	`}`
`},`	`},`
`'type' => 'num',`
`'value' => 1,`	`'value' => 1,`
`'connection_num' => undef`	`'type' => 'num'`
	`}`
	`},`
	`'description_pdf' => undef,`
	`'module_name' => 'TOP',`
	`'category' => 'TOP',`
	`'module' => 'TOP',`
	`'instance_name' => 'TOP',`
	`'parameters_order' => [],`
	`'sockets' => {}`
	`}`
	`},`
	`'modules' => {},`
	`'soc_name' => {`
	`'TOP' => undef`
`},`	`},`
	`'device_win_adj' => {},`
	`'gui_status' => {`
	`'timeout' => 0,`
	`'status' => 'ideal'`
	`},`
	`'SOURCE_SET' => {`
	`'IP' => bless( {`
	`'plugs' => {`
`'reset' => {`	`'reset' => {`
	`'type' => 'num',`
`'value' => 1,`	`'value' => 1,`
	`'0' => {`
	`'name' => 'source_reset_in'`
	`},`
	`'1' => {}`
	`},`
	`'clk' => {`
`'type' => 'num',`	`'type' => 'num',`
`'nums' => {`	`'value' => 1,`
`'0' => {`	`'0' => {`
`'connect_id' => 'clk_source0',`	`'name' => 'source_clk_in'`
`'name' => 'reset',`
`'connect_socket_num' => '0',`
`'connect_socket' => 'reset'`
`}`
`},`	`},`
`'connection_num' => undef`	`'1' => {}`
`}`	`}`
`},`	`},`
`'module_name' => 'wb_single_port_ram',`	`'hdl_files' => [],`
`'instance_name' => 'ram'`	`'file_name' => undef,`
	`'module_name' => 'TOP',`
	`'category' => 'TOP',`
	`'GUI_REMOVE_SET' => 'DISABLE',`
	`'parameters_order' => [],`
	`'ports' => {`
	`'source_clk_in' => {`
	`'intfc_port' => 'clk_i',`
	`'type' => 'input',`
	`'intfc_name' => 'plug:clk[0]',`
	`'range' => undef`
	`},`
	`'source_reset_in' => {`
	`'range' => undef,`
	`'intfc_port' => 'reset_i',`
	`'type' => 'input',`
	`'intfc_name' => 'plug:reset[0]'`
`}`	`}`
`},`	`},`
`'compile' => {`	`'ports_order' => [],`
`'modelsim_bin' => '/home/alireza/intelFPGA_lite/questa/questasim/bin',`	`'ip_name' => 'TOP',`
`'type' => 'Modelsim',`	`'hdl_files_ticked' => []`
`'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin',`	`}, 'ip_gen' )`
`'board' => 'DE5',`	`},`
`'compilers' => 'QuartusII,Vivado,Verilator,Modelsim'`	`'hdl_files_ticked' => undef`
	`}, 'soc' )`
	`},`
	`'timer0' => {`
	`'version' => 12`
`},`	`},`
`'hdl_files' => undef,`	`'ProNoC_jtag_uart0' => {`
`'gui_status' => {`	`'version' => 11`
`'timeout' => 0,`	`},`
`'status' => 'save_project'`	`'compile_pin_range_hsb' => {},`
	`'current_module_param_type' => undef,`
	`'ni_master0' => {`
	`'version' => 84`
`},`	`},`
`'top_ip' => bless( {`	`'top_ip' => bless( {`
`'interface' => {`
`'socket:ni[0]' => {`
`'ports' => {`	`'ports' => {`
`'ni_current_r_addr' => {`	`'ni_chan_out' => {`
`'intfc_port' => 'current_r_addr',`	`'intfc_name' => 'socket:ni[0]',`
`'type' => 'input',`	`'intfc_port' => 'chan_out',`
`'instance_name' => 'ni_master0',`	`'type' => 'output',`
`'range' => 'ni_RAw-1 : 0'`
`},`
`'ni_chan_in' => {`
`'range' => 'smartflit_chanel_t',`	`'range' => 'smartflit_chanel_t',`
`'intfc_port' => 'chan_in',`	`'instance_name' => 'ni_master0'`
`'instance_name' => 'ni_master0',`
`'type' => 'input'`
`},`	`},`
`'ni_current_e_addr' => {`	`'ni_current_e_addr' => {`
	`'intfc_name' => 'socket:ni[0]',`
`'intfc_port' => 'current_e_addr',`	`'intfc_port' => 'current_e_addr',`
`'type' => 'input',`	`'type' => 'input',`
`'instance_name' => 'ni_master0',`	`'instance_name' => 'ni_master0',`
`'range' => 'ni_EAw-1 : 0'`	`'range' => 'ni_EAw-1 : 0'`
`},`	`},`
`'ni_chan_out' => {`	`'source_clk_in' => {`
`'range' => 'smartflit_chanel_t',`	`'type' => 'input',`
`'instance_name' => 'ni_master0',`	`'intfc_port' => 'clk_i',`
`'intfc_port' => 'chan_out',`	`'intfc_name' => 'plug:clk[0]',`
	`'instance_name' => 'clk_source0',`
	`'range' => ''`
	`},`
	`'uart_wb_to_jtag' => {`
	`'range' => 'uart_WB2Jw-1 : 0',`
	`'instance_name' => 'ProNoC_jtag_uart0',`
	`'intfc_port' => 'jwb_o',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'type' => 'output'`	`'type' => 'output'`
`}`
`}`
`},`	`},`
`'socket:RxD_sim[0]' => {`	`'cpu_cpu_en' => {`
`'ports' => {`	`'instance_name' => 'mor1kx0',`
`'uart_RxD_wr_sim' => {`	`'range' => '',`
	`'type' => 'input',`
	`'intfc_port' => 'enable_i',`
	`'intfc_name' => 'plug:enable[0]'`
	`},`
	`'ram_wb_to_jtag' => {`
	`'range' => 'ram_WB2Jw-1 : 0',`
	`'instance_name' => 'single_port_ram0',`
	`'intfc_port' => 'jwb_o',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'type' => 'output'`
	`},`
	`'uart_jtag_to_wb' => {`
	`'intfc_port' => 'jwb_i',`
	`'type' => 'input',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'instance_name' => 'ProNoC_jtag_uart0',`	`'instance_name' => 'ProNoC_jtag_uart0',`
`'intfc_port' => 'RxD_wr_sim',`	`'range' => 'uart_J2WBw-1 : 0'`
	`},`
	`'source_reset_in' => {`
`'type' => 'input',`	`'type' => 'input',`
	`'intfc_port' => 'reset_i',`
	`'intfc_name' => 'plug:reset[0]',`
	`'instance_name' => 'clk_source0',`
`'range' => ''`	`'range' => ''`
`},`	`},`
`'uart_RxD_din_sim' => {`	`'uart_RxD_din_sim' => {`
`'instance_name' => 'ProNoC_jtag_uart0',`	`'instance_name' => 'ProNoC_jtag_uart0',`
	`'range' => '7:0 ',`
	`'intfc_name' => 'socket:RxD_sim[0]',`
`'intfc_port' => 'RxD_din_sim',`	`'intfc_port' => 'RxD_din_sim',`
	`'type' => 'input'`
	`},`
	`'ram_jtag_to_wb' => {`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'intfc_port' => 'jwb_i',`
`'type' => 'input',`	`'type' => 'input',`
`'range' => '7:0 '`	`'range' => 'ram_J2WBw-1 : 0',`
	`'instance_name' => 'single_port_ram0'`
	`},`
	`'ni_chan_in' => {`
	`'range' => 'smartflit_chanel_t',`
	`'instance_name' => 'ni_master0',`
	`'intfc_port' => 'chan_in',`
	`'type' => 'input',`
	`'intfc_name' => 'socket:ni[0]'`
	`},`
	`'uart_RxD_wr_sim' => {`
	`'intfc_port' => 'RxD_wr_sim',`
	`'type' => 'input',`
	`'intfc_name' => 'socket:RxD_sim[0]',`
	`'range' => '',`
	`'instance_name' => 'ProNoC_jtag_uart0'`
	`},`
	`'ni_current_r_addr' => {`
	`'range' => 'ni_RAw-1 : 0',`
	`'instance_name' => 'ni_master0',`
	`'intfc_name' => 'socket:ni[0]',`
	`'intfc_port' => 'current_r_addr',`
	`'type' => 'input'`
`},`	`},`
`'uart_RxD_ready_sim' => {`	`'uart_RxD_ready_sim' => {`
`'intfc_port' => 'RxD_ready_sim',`	`'intfc_port' => 'RxD_ready_sim',`
`'instance_name' => 'ProNoC_jtag_uart0',`	`'intfc_name' => 'socket:RxD_sim[0]',`
`'type' => 'output',`	`'type' => 'output',`
	`'instance_name' => 'ProNoC_jtag_uart0',`
`'range' => ''`	`'range' => ''`
`}`	`}`
`}`
`},`	`},`
`'plug:clk[0]' => {`	`'interface' => {`
	`'socket:ni[0]' => {`
`'ports' => {`	`'ports' => {`
`'source_clk_in' => {`	`'ni_chan_out' => {`
`'range' => '',`	`'instance_name' => 'ni_master0',`
`'intfc_port' => 'clk_i',`	`'range' => 'smartflit_chanel_t',`
	`'type' => 'output',`
	`'intfc_port' => 'chan_out'`
	`},`
	`'ni_current_e_addr' => {`
	`'range' => 'ni_EAw-1 : 0',`
	`'instance_name' => 'ni_master0',`
	`'intfc_port' => 'current_e_addr',`
	`'type' => 'input'`
	`},`
	`'ni_current_r_addr' => {`
	`'range' => 'ni_RAw-1 : 0',`
	`'instance_name' => 'ni_master0',`
	`'type' => 'input',`
	`'intfc_port' => 'current_r_addr'`
	`},`
	`'ni_chan_in' => {`
`'type' => 'input',`	`'type' => 'input',`
`'instance_name' => 'clk_source0'`	`'intfc_port' => 'chan_in',`
	`'range' => 'smartflit_chanel_t',`
	`'instance_name' => 'ni_master0'`
`}`	`}`
`}`	`}`
`},`	`},`
`'plug:enable[0]' => {`	`'socket:RxD_sim[0]' => {`
`'ports' => {`	`'ports' => {`
`'cpu_cpu_en' => {`	`'uart_RxD_wr_sim' => {`
`'instance_name' => 'mor1kx0',`
`'intfc_port' => 'enable_i',`
`'type' => 'input',`	`'type' => 'input',`
`'range' => ''`	`'intfc_port' => 'RxD_wr_sim',`
	`'range' => '',`
	`'instance_name' => 'ProNoC_jtag_uart0'`
	`},`
	`'uart_RxD_ready_sim' => {`
	`'instance_name' => 'ProNoC_jtag_uart0',`
	`'range' => '',`
	`'type' => 'output',`
	`'intfc_port' => 'RxD_ready_sim'`
	`},`
	`'uart_RxD_din_sim' => {`
	`'type' => 'input',`
	`'intfc_port' => 'RxD_din_sim',`
	`'range' => '7:0 ',`
	`'instance_name' => 'ProNoC_jtag_uart0'`
`}`	`}`
`}`	`}`
`},`	`},`
`'socket:jtag_to_wb[0]' => {`	`'socket:jtag_to_wb[0]' => {`
`'ports' => {`	`'ports' => {`
`'ram_wb_to_jtag' => {`
`'intfc_port' => 'jwb_o',`
`'type' => 'output',`
`'instance_name' => 'single_port_ram0',`
`'range' => 'ram_WB2Jw-1 : 0'`
`},`
`'uart_wb_to_jtag' => {`	`'uart_wb_to_jtag' => {`
`'range' => 'uart_WB2Jw-1 : 0',`
`'type' => 'output',`	`'type' => 'output',`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'instance_name' => 'ProNoC_jtag_uart0'`	`'instance_name' => 'ProNoC_jtag_uart0',`
`},`	`'range' => 'uart_WB2Jw-1 : 0'`
`'uart_jtag_to_wb' => {`
`'range' => 'uart_J2WBw-1 : 0',`
`'intfc_port' => 'jwb_i',`
`'type' => 'input',`
`'instance_name' => 'ProNoC_jtag_uart0'`
`},`	`},`
`'ram_jtag_to_wb' => {`	`'ram_jtag_to_wb' => {`
	`'range' => 'ram_J2WBw-1 : 0',`
	`'instance_name' => 'single_port_ram0',`
`'intfc_port' => 'jwb_i',`	`'intfc_port' => 'jwb_i',`
	`'type' => 'input'`
	`},`
	`'uart_jtag_to_wb' => {`
`'type' => 'input',`	`'type' => 'input',`
	`'intfc_port' => 'jwb_i',`
	`'instance_name' => 'ProNoC_jtag_uart0',`
	`'range' => 'uart_J2WBw-1 : 0'`
	`},`
	`'ram_wb_to_jtag' => {`
	`'range' => 'ram_WB2Jw-1 : 0',`
`'instance_name' => 'single_port_ram0',`	`'instance_name' => 'single_port_ram0',`
`'range' => 'ram_J2WBw-1 : 0'`	`'intfc_port' => 'jwb_o',`
	`'type' => 'output'`
`}`	`}`
`}`	`}`
`},`	`},`
`'plug:reset[0]' => {`	`'plug:clk[0]' => {`
`'ports' => {`	`'ports' => {`
`'source_reset_in' => {`	`'source_clk_in' => {`
`'instance_name' => 'clk_source0',`	`'instance_name' => 'clk_source0',`
`'intfc_port' => 'reset_i',`	`'range' => '',`
`'type' => 'input',`	`'type' => 'input',`
`'range' => ''`	`'intfc_port' => 'clk_i'`
`}`
`}`	`}`
`}`	`}`
`},`	`},`
`'instance_ids' => {`	`'plug:reset[0]' => {`
`'ProNoC_jtag_uart0' => {`
`'instance' => 'uart',`
`'ports' => {`	`'ports' => {`
`'uart_RxD_ready_sim' => {`	`'source_reset_in' => {`
`'intfc_name' => 'socket:RxD_sim[0]',`	`'instance_name' => 'clk_source0',`
`'range' => '',`	`'range' => '',`
`'intfc_port' => 'RxD_ready_sim',`
`'type' => 'output'`
`},`
`'uart_jtag_to_wb' => {`
`'intfc_port' => 'jwb_i',`
`'type' => 'input',`	`'type' => 'input',`
`'range' => 'uart_J2WBw-1 : 0',`	`'intfc_port' => 'reset_i'`
`'intfc_name' => 'socket:jtag_to_wb[0]'`	`}`
`},`	`}`
`'uart_RxD_din_sim' => {`
`'intfc_name' => 'socket:RxD_sim[0]',`
`'range' => '7:0 ',`
`'type' => 'input',`
`'intfc_port' => 'RxD_din_sim'`
`},`
`'uart_wb_to_jtag' => {`
`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'uart_WB2Jw-1 : 0',`
`'type' => 'output',`
`'intfc_port' => 'jwb_o'`
`},`	`},`
`'uart_RxD_wr_sim' => {`	`'plug:enable[0]' => {`
`'type' => 'input',`	`'ports' => {`
`'intfc_port' => 'RxD_wr_sim',`	`'cpu_cpu_en' => {`
	`'instance_name' => 'mor1kx0',`
`'range' => '',`	`'range' => '',`
`'intfc_name' => 'socket:RxD_sim[0]'`	`'intfc_port' => 'enable_i',`
	`'type' => 'input'`
	`}`
	`}`
`}`	`}`
`},`	`},`
`'module_name' => 'pronoc_jtag_uart',`	`'instance_ids' => {`
	`'wishbone_bus0' => {`
	`'module' => 'wishbone_bus',`
	`'instance' => 'bus',`
`'localparam' => {`	`'localparam' => {`
`'uart_TAGw' => {`	`'bus_Aw' => {`
`'content' => '',`
`'info' => 'Parameter',`
`'type' => 'Fixed',`
`'default' => '3',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1`
`},`
`'uart_SELw' => {`
`'info' => 'Parameter',`
`'content' => '',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'default' => '4',`
`'type' => 'Fixed'`
`},`
`'uart_Aw' => {`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'default' => '1',`
`'type' => 'Fixed',`
`'info' => 'Parameter',`
`'content' => ''`
`},`
`'uart_BUFF_Aw' => {`
`'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',`
`'content' => '2,16,1',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'default' => '4',`	`'info' => 'The wishbone Bus address width',`
`'type' => 'Spin-button'`	`'content' => '4,128,1',`
	`'type' => 'Spin-button',`
	`'default' => '32'`
`},`	`},`
`'uart_Dw' => {`	`'bus_SELw' => {`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'default' => '32',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'info' => 'Parameter',`	`'default' => 'bus_Dw/8',`
`'content' => ''`
`}`
`},`
`'module' => 'ProNoC_jtag_uart',`
`'parameters' => {`
`'uart_JINDEXw' => {`
`'info' => 'Parameter',`
`'content' => '',`
`'global_param' => 'Parameter',`
`'redefine_param' => 1,`
`'default' => '8',`
`'type' => 'Fixed'`
`},`
`'uart_JAw' => {`
`'content' => '',`	`'content' => '',`
`'info' => 'Parameter',`	`'info' => undef`
`'default' => '32',`
`'type' => 'Fixed',`
`'global_param' => 'Parameter',`
`'redefine_param' => 1`
`},`	`},`
`'uart_JTAG_INDEX' => {`	`'bus_S' => {`
`'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',`	`'content' => '1,256,1',`
`'content' => '',`	`'info' => 'Number of wishbone slave interface',`
	`'default' => '4',`
	`'type' => 'Spin-button',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter',`	`'global_param' => 'Localparam'`
`'type' => 'Entry',`
`'default' => '126-CORE_ID'`
`},`
`'uart_JTAG_CHAIN' => {`
`'content' => '1,2,3,4',`
`'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:`
`4: JTAG runtime memory programmers.`
`3: UART`
`1,2: reserved',`
`'default' => '3',`
`'type' => 'Combo-box',`
`'redefine_param' => 0,`
`'global_param' => 'Parameter'`
`},`	`},`
`'uart_WB2Jw' => {`	`'bus_M' => {`
`'content' => '',`	`'global_param' => 'Localparam',`
`'info' => '',`	`'redefine_param' => 1,`
`'type' => 'Fixed',`	`'type' => 'Spin-button',`
`'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`	`'default' => ' 4',`
`'global_param' => 'Parameter',`	`'content' => '1,256,1',`
`'redefine_param' => 1`	`'info' => 'Number of wishbone master interface'`
`},`	`},`
`'uart_JSTATUSw' => {`	`'bus_TAGw' => {`
`'info' => 'Parameter',`
`'content' => '',`	`'content' => '',`
`'global_param' => 'Parameter',`	`'info' => undef,`
`'redefine_param' => 1,`	`'default' => '3',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '8'`
`},`
`'uart_JTAG_CONNECT' => {`
`'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',`
`'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.`

`For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',`
`'default' => '"ALTERA_JTAG_WB"',`
`'type' => 'Combo-box',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter'`	`'global_param' => 'Localparam'`
`},`	`},`
`'uart_J2WBw' => {`	`'bus_CTIw' => {`
	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter',`	`'default' => '3',`
`'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'info' => undef,`	`'info' => undef,`
`'content' => ''`	`'content' => ''`
`},`	`},`
`'uart_JDw' => {`	`'bus_BTEw' => {`
	`'redefine_param' => 1,`
	`'global_param' => 'Localparam',`
	`'info' => undef,`
`'content' => '',`	`'content' => '',`
`'info' => 'Parameter',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
	`'default' => '2 '`
	`},`
	`'bus_Dw' => {`
	`'content' => '8,512,8',`
	`'info' => 'The wishbone Bus data width in bits.',`
`'default' => '32',`	`'default' => '32',`
	`'type' => 'Spin-button',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter'`	`'global_param' => 'Localparam'`
`}`	`}`
`},`	`},`
`'category' => 'Communication'`	`'category' => 'Bus',`
	`'module_name' => 'wishbone_bus'`
`},`	`},`
`'timer0' => {`	`'timer0' => {`
`'module' => 'timer',`	`'module_name' => 'timer',`
	`'category' => 'Timer',`
`'localparam' => {`	`'localparam' => {`
`'timer_Aw' => {`	`'timer_Aw' => {`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '3',`	`'default' => '3',`
`'info' => undef,`
`'content' => ''`
`},`
`'timer_CNTw' => {`
`'info' => undef,`
`'content' => '',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`
`'type' => 'Fixed',`
`'default' => '32 '`
`},`
`'timer_SELw' => {`
`'default' => '4',`
`'type' => 'Fixed',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'content' => '',`	`'content' => '',`
`'info' => undef`	`'info' => undef`
`},`	`},`
`'timer_TAGw' => {`
`'info' => undef,`
`'content' => '',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'default' => '3',`
`'type' => 'Fixed'`
`},`
`'timer_PRESCALER_WIDTH' => {`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`
`'type' => 'Spin-button',`
`'default' => '8',`
`'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.`


`',`
`'content' => '1,32,1'`
`},`
`'timer_Dw' => {`	`'timer_Dw' => {`
`'content' => '',`
`'info' => undef,`	`'info' => undef,`
`'type' => 'Fixed',`	`'content' => '',`
`'default' => '32',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1`
`}`
`},`
`'category' => 'Timer',`
`'instance' => 'timer',`
`'module_name' => 'timer'`
`},`
`'wishbone_bus0' => {`
`'instance' => 'bus',`
`'module_name' => 'wishbone_bus',`
`'category' => 'Bus',`
`'localparam' => {`
`'bus_Dw' => {`
`'info' => 'The wishbone Bus data width in bits.',`
`'content' => '8,512,8',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`
`'type' => 'Spin-button',`
`'default' => '32'`
`},`
`'bus_Aw' => {`
`'default' => '32',`	`'default' => '32',`
`'type' => 'Spin-button',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`
`'content' => '4,128,1',`
`'info' => 'The wishbone Bus address width'`
`},`
`'bus_BTEw' => {`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '2 ',`	`'redefine_param' => 1,`
`'info' => undef,`	`'global_param' => 'Localparam'`
`'content' => ''`
`},`	`},`
`'bus_CTIw' => {`	`'timer_CNTw' => {`
`'content' => '',`	`'content' => '',`
`'info' => undef,`	`'info' => undef,`
	`'default' => '32 ',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '3',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam'`	`'global_param' => 'Localparam'`
`},`	`},`
`'bus_SELw' => {`	`'timer_TAGw' => {`
	`'default' => '3',`
	`'type' => 'Fixed',`
`'info' => undef,`	`'info' => undef,`
`'content' => '',`	`'content' => '',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'default' => 'bus_Dw/8',`
`'type' => 'Fixed'`
`},`
`'bus_S' => {`
`'info' => 'Number of wishbone slave interface',`
`'content' => '1,256,1',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`
`'default' => '4',`
`'type' => 'Spin-button'`
`},`
`'bus_M' => {`
`'content' => '1,256,1',`
`'info' => 'Number of wishbone master interface',`
`'default' => ' 4',`
`'type' => 'Spin-button',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1`	`'redefine_param' => 1`
`},`	`},`
`'bus_TAGw' => {`	`'timer_SELw' => {`
`'content' => '',`	`'content' => '',`
`'info' => undef,`	`'info' => undef,`
`'default' => '3',`	`'default' => '4',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam'`	`'global_param' => 'Localparam'`
`}`
`},`
`'module' => 'wishbone_bus'`
`},`	`},`
`'clk_source0' => {`	`'timer_PRESCALER_WIDTH' => {`
`'category' => 'Source',`
`'localparam' => {`
`'source_FPGA_VENDOR' => {`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'default' => '"ALTERA"',`	`'global_param' => 'Localparam',`
`'type' => 'Combo-box',`	`'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.`
`'info' => '',`
`'content' => '"ALTERA","XILINX"'`
`}`	`',`
`},`	`'content' => '1,32,1',`
`'module' => 'clk_source',`	`'type' => 'Spin-button',`
`'module_name' => 'clk_source',`	`'default' => '8'`
`'ports' => {`
`'source_clk_in' => {`
`'intfc_port' => 'clk_i',`
`'type' => 'input',`
`'intfc_name' => 'plug:clk[0]',`
`'range' => ''`
`},`
`'source_reset_in' => {`
`'intfc_port' => 'reset_i',`
`'type' => 'input',`
`'range' => '',`
`'intfc_name' => 'plug:reset[0]'`
`}`	`}`
`},`	`},`
`'instance' => 'source'`	`'module' => 'timer',`
	`'instance' => 'timer'`
`},`	`},`
`'ni_master0' => {`	`'ni_master0' => {`
`'category' => 'NoC',`
`'localparam' => {`	`'localparam' => {`
`'ni_CRC_EN' => {`	`'ni_CRC_EN' => {`
`'default' => '"NO"',`
`'type' => 'Combo-box',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'content' => '"YES","NO"',`	`'redefine_param' => 1,`
	`'type' => 'Combo-box',`
	`'default' => '"NO"',`
`'info' => 'The parameter can be selected as "YES" or "NO".`	`'info' => 'The parameter can be selected as "YES" or "NO".`
`If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. '`	`If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',`
	`'content' => '"YES","NO"'`
	`},`
	`'ni_TAGw' => {`
	`'info' => 'Parameter',`
	`'content' => '',`
	`'default' => '3',`
	`'type' => 'Fixed',`
	`'redefine_param' => 1,`
	`'global_param' => 'Localparam'`
`},`	`},`
`'ni_Dw' => {`	`'ni_Dw' => {`
`'info' => 'wishbone_bus data width in bits.',`	`'type' => 'Spin-button',`
	`'default' => '32',`
`'content' => '32,256,8',`	`'content' => '32,256,8',`
`'redefine_param' => 1,`	`'info' => 'wishbone_bus data width in bits.',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'type' => 'Spin-button',`	`'redefine_param' => 1`
`'default' => '32'`
`},`	`},`
`'ni_HDATA_PRECAPw' => {`	`'ni_HDATA_PRECAPw' => {`
	`'redefine_param' => 1,`
	`'global_param' => 'Localparam',`
`'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',`	`'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',`
`'content' => '0,8,1',`	`'content' => '0,8,1',`
	`'type' => 'Spin-button',`
	`'default' => '0'`
	`},`
	`'ni_S_Aw' => {`
	`'default' => '8',`
	`'type' => 'Fixed',`
	`'content' => '',`
	`'info' => 'Parameter',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1`
`'default' => '0',`
`'type' => 'Spin-button'`
`},`	`},`
`'ni_MAX_BURST_SIZE' => {`	`'ni_M_Aw' => {`
`'info' => 'Maximum burst size in words.`	`'default' => '32',`
`The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',`	`'type' => 'Fixed',`
`'content' => '2,4,8,16,32,64,128,256,512,1024,2048',`	`'info' => 'Parameter',`
`'redefine_param' => 1,`	`'content' => 'Dw',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'default' => '16',`	`'redefine_param' => 1`
`'type' => 'Combo-box'`
`},`	`},`
`'ni_MAX_TRANSACTION_WIDTH' => {`	`'ni_MAX_TRANSACTION_WIDTH' => {`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'type' => 'Spin-button',`	`'type' => 'Spin-button',`
`'default' => '13',`	`'default' => '13',`
`'info' => 'maximum packet size width in words.`	`'info' => 'maximum packet size width in words.`
`The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',`	`The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',`
`'content' => '4,32,1'`	`'content' => '4,32,1'`
`},`	`},`
`'ni_M_Aw' => {`	`'ni_MAX_BURST_SIZE' => {`
`'redefine_param' => 1,`	`'content' => '2,4,8,16,32,64,128,256,512,1024,2048',`
`'global_param' => 'Localparam',`	`'info' => 'Maximum burst size in words.`
`'type' => 'Fixed',`	`The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',`
`'default' => '32',`	`'type' => 'Combo-box',`
`'info' => 'Parameter',`	`'default' => '16',`
`'content' => 'Dw'`
`},`
`'ni_S_Aw' => {`
`'default' => '8',`
`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam'`
`'content' => '',`
`'info' => 'Parameter'`
`},`	`},`
`'ni_SELw' => {`	`'ni_SELw' => {`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'type' => 'Fixed',`	`'redefine_param' => 1,`
`'default' => '4',`	`'default' => '4',`
	`'type' => 'Fixed',`
`'info' => 'Parameter',`	`'info' => 'Parameter',`
`'content' => ''`	`'content' => ''`
`},`
`'ni_TAGw' => {`
`'info' => 'Parameter',`
`'content' => '',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'default' => '3',`
`'type' => 'Fixed'`
`}`	`}`
`},`	`},`
`'parameters' => {`	`'parameters' => {`
`'ni_EAw' => {`	`'ni_RAw' => {`
`'redefine_param' => 0,`
`'global_param' => 'Parameter',`	`'global_param' => 'Parameter',`
`'default' => '16',`	`'redefine_param' => 0,`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'info' => undef,`	`'default' => '16',`
`'content' => ''`	`'content' => '',`
	`'info' => undef`
`},`	`},`
`'ni_RAw' => {`	`'ni_EAw' => {`
`'info' => undef,`	`'type' => 'Fixed',`
	`'default' => '16',`
`'content' => '',`	`'content' => '',`
`'redefine_param' => 0,`	`'info' => undef,`
`'global_param' => 'Parameter',`	`'global_param' => 'Parameter',`
`'type' => 'Fixed',`	`'redefine_param' => 0`
`'default' => '16'`
`}`	`}`
`},`	`},`
`'module' => 'ni_master',`	`'module' => 'ni_master',`
`'instance' => 'ni',`	`'instance' => 'ni',`
`'ports' => {`	`'ports' => {`
`'ni_current_e_addr' => {`	`'ni_chan_out' => {`
`'range' => 'ni_EAw-1 : 0',`	`'range' => 'smartflit_chanel_t',`
`'intfc_name' => 'socket:ni[0]',`	`'intfc_name' => 'socket:ni[0]',`
`'type' => 'input',`	`'intfc_port' => 'chan_out',`
`'intfc_port' => 'current_e_addr'`	`'type' => 'output'`
`},`	`},`
`'ni_chan_in' => {`	`'ni_current_r_addr' => {`
	`'range' => 'ni_RAw-1 : 0',`
`'type' => 'input',`	`'type' => 'input',`
`'intfc_port' => 'chan_in',`	`'intfc_port' => 'current_r_addr',`
`'range' => 'smartflit_chanel_t',`
`'intfc_name' => 'socket:ni[0]'`	`'intfc_name' => 'socket:ni[0]'`
`},`	`},`
`'ni_chan_out' => {`	`'ni_current_e_addr' => {`
`'intfc_port' => 'chan_out',`	`'range' => 'ni_EAw-1 : 0',`
`'type' => 'output',`	`'intfc_port' => 'current_e_addr',`
`'intfc_name' => 'socket:ni[0]',`	`'intfc_name' => 'socket:ni[0]',`
`'range' => 'smartflit_chanel_t'`	`'type' => 'input'`
`},`	`},`
`'ni_current_r_addr' => {`	`'ni_chan_in' => {`
`'range' => 'ni_RAw-1 : 0',`	`'range' => 'smartflit_chanel_t',`
	`'intfc_port' => 'chan_in',`
`'intfc_name' => 'socket:ni[0]',`	`'intfc_name' => 'socket:ni[0]',`
`'type' => 'input',`	`'type' => 'input'`
`'intfc_port' => 'current_r_addr'`
`}`	`}`
`},`	`},`
	`'category' => 'NoC',`
`'module_name' => 'ni_master'`	`'module_name' => 'ni_master'`
`},`	`},`
`'single_port_ram0' => {`	`'clk_source0' => {`
`'category' => 'RAM',`	`'ports' => {`
	`'source_reset_in' => {`
	`'range' => '',`
	`'intfc_port' => 'reset_i',`
	`'type' => 'input',`
	`'intfc_name' => 'plug:reset[0]'`
	`},`
	`'source_clk_in' => {`
	`'range' => '',`
	`'type' => 'input',`
	`'intfc_port' => 'clk_i',`
	`'intfc_name' => 'plug:clk[0]'`
	`}`
	`},`
	`'instance' => 'source',`
	`'module' => 'clk_source',`
	`'module_name' => 'clk_source',`
	`'category' => 'Source',`
`'localparam' => {`	`'localparam' => {`
`'ram_INIT_FILE_PATH' => {`	`'source_FPGA_VENDOR' => {`
	`'redefine_param' => 1,`
	`'global_param' => 'Localparam',`
	`'content' => '"ALTERA","XILINX"',`
	`'info' => '',`
	`'default' => '"ALTERA"',`
	`'type' => 'Combo-box'`
	`}`
	`}`
	`},`
	`'single_port_ram0' => {`
	`'parameters' => {`
	`'ram_JTAG_INDEX' => {`
	`'redefine_param' => 1,`
	`'global_param' => 'Parameter',`
	`'content' => '',`
	`'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.`

	`In case you have \'n\' memory in each processing core you can define their index as "nCORE_ID+1 , nCORE_ID+2 ...n*CORE_ID+n-1).`

	`You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).`

	`',`
	`'type' => 'Entry',`
	`'default' => 'CORE_ID'`
	`},`
	`'ram_JINDEXw' => {`
	`'type' => 'Fixed',`
	`'default' => '8',`
	`'info' => 'Parameter',`
	`'content' => '',`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1`
	`},`
	`'ram_JDw' => {`
	`'default' => 'ram_Dw',`
	`'type' => 'Fixed',`
	`'content' => '',`
	`'info' => 'Parameter',`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1`
	`},`
	`'ram_JTAG_CHAIN' => {`
	`'redefine_param' => 0,`
	`'global_param' => 'Parameter',`
	`'content' => '1,2,3,4',`
	`'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:`
	`4: JTAG runtime memory programmers.`
	`3: UART`
	`1,2: reserved',`
	`'default' => '4',`
	`'type' => 'Combo-box'`
	`},`
	`'ram_WB2Jw' => {`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1,`
	`'type' => 'Fixed',`
	`'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`
	`'content' => '',`
	`'info' => undef`
	`},`
	`'ram_J2WBw' => {`
	`'content' => '',`
`'info' => undef,`	`'info' => undef,`
	`'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`
	`'type' => 'Fixed',`
	`'redefine_param' => 1,`
	`'global_param' => 'Parameter'`
	`},`
	`'ram_JAw' => {`
	`'type' => 'Fixed',`
	`'default' => '32',`
	`'info' => 'Parameter',`
`'content' => '',`	`'content' => '',`
`'global_param' => 'Localparam',`	`'global_param' => 'Parameter',`
	`'redefine_param' => 1`
	`},`
	`'ram_JSTATUSw' => {`
	`'info' => 'Parameter',`
	`'content' => '',`
	`'default' => '8',`
	`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'default' => 'SW_LOC',`	`'global_param' => 'Parameter'`
`'type' => 'Fixed'`
`},`	`},`
`'ram_INITIAL_EN' => {`	`'ram_Dw' => {`
`'content' => '"YES","NO"',`	`'redefine_param' => 1,`
`'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',`	`'global_param' => 'Parameter',`
	`'info' => 'Memory data width in Bits.',`
	`'content' => '8,1024,1',`
	`'default' => '32',`
	`'type' => 'Spin-button'`
	`},`
	`'ram_JTAG_CONNECT' => {`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1,`
`'type' => 'Combo-box',`	`'type' => 'Combo-box',`
`'default' => '"YES"',`	`'default' => '"ALTERA_JTAG_WB"',`
`'global_param' => 'Localparam',`	`'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',`
`'redefine_param' => 1`	`'info' => 'JTAG_CONNECT:`
	`if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '`
	`}`
`},`	`},`
	`'localparam' => {`
`'ram_WB_Aw' => {`	`'ram_WB_Aw' => {`
`'type' => 'Spin-button',`	`'type' => 'Spin-button',`
`'default' => '20',`	`'default' => '20',`
	`'content' => '4,31,1',`
	`'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
	`},`
	`'ram_Aw' => {`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
	`'global_param' => 'Localparam',`
`'content' => '4,31,1',`	`'content' => '4,31,1',`
`'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). '`	`'info' => 'Memory address width',`
	`'type' => 'Spin-button',`
	`'default' => '14'`
	`},`
	`'ram_SELw' => {`
	`'type' => 'Fixed',`
	`'default' => 'ram_Dw/8',`
	`'info' => 'Parameter',`
	`'content' => '',`
	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
	`},`
	`'ram_FPGA_VENDOR' => {`
	`'redefine_param' => 1,`
	`'global_param' => 'Localparam',`
	`'content' => '"ALTERA","XILINX","GENERIC"',`
	`'info' => '',`
	`'default' => '"ALTERA"',`
	`'type' => 'Combo-box'`
`},`	`},`
`'ram_Aw' => {`	`'ram_BTEw' => {`
`'content' => '4,31,1',`	`'default' => '2',`
`'info' => 'Memory address width',`	`'type' => 'Fixed',`
`'default' => '14',`	`'content' => '',`
`'type' => 'Spin-button',`	`'info' => 'Parameter',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1`	`'redefine_param' => 1`
`},`	`},`
`'ram_MEM_CONTENT_FILE_NAME' => {`	`'ram_MEM_CONTENT_FILE_NAME' => {`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'type' => 'Entry',`	`'global_param' => 'Localparam',`
`'default' => '"ram0"',`	`'content' => '',`
`'info' => 'MEM_FILE_NAME:`	`'info' => 'MEM_FILE_NAME:`
`The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.`	`The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.`

`File Path:`	`File Path:`
`For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.`	`For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.`
Line 1934...	Line 2040...

`file_type:`	`file_type:`
`bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.`	`bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.`
`memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.`	`memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.`
`mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',`	`mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',`
`'content' => ''`	`'type' => 'Entry',`
	`'default' => '"ram0"'`
`},`	`},`
`'ram_BURST_MODE' => {`	`'ram_BYTE_WR_EN' => {`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'type' => 'Combo-box',`	`'content' => '"YES","NO"',`
`'default' => '"ENABLED"',`	`'info' => 'Byte enable',`
`'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',`	`'default' => '"YES"',`
`'content' => '"DISABLED","ENABLED"'`	`'type' => 'Combo-box'`
`},`	`},`
`'ram_BTEw' => {`	`'ram_TAGw' => {`
`'info' => 'Parameter',`
`'content' => '',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'default' => '2',`
`'type' => 'Fixed'`
`},`
`'ram_CTIw' => {`
`'content' => '',`
`'info' => 'Parameter',`	`'info' => 'Parameter',`
	`'content' => '',`
`'default' => '3',`	`'default' => '3',`
`'type' => 'Fixed',`	`'type' => 'Fixed'`
	`},`
	`'ram_BURST_MODE' => {`
	`'type' => 'Combo-box',`
	`'default' => '"ENABLED"',`
	`'content' => '"DISABLED","ENABLED"',`
	`'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1`	`'redefine_param' => 1`
`},`	`},`
`'ram_SELw' => {`	`'ram_INIT_FILE_PATH' => {`
`'info' => 'Parameter',`	`'type' => 'Fixed',`
	`'default' => 'SW_LOC',`
	`'info' => undef,`
`'content' => '',`	`'content' => '',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'default' => 'ram_Dw/8',`	`'redefine_param' => 1`
`'type' => 'Fixed'`
`},`	`},`
`'ram_TAGw' => {`	`'ram_INITIAL_EN' => {`
`'info' => 'Parameter',`
`'content' => '',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'default' => '3',`
`'type' => 'Fixed'`
`},`
`'ram_BYTE_WR_EN' => {`
`'content' => '"YES","NO"',`
`'info' => 'Byte enable',`
`'default' => '"YES"',`	`'default' => '"YES"',`
`'type' => 'Combo-box',`	`'type' => 'Combo-box',`
	`'content' => '"YES","NO"',`
	`'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'`
	`},`
	`'ram_CTIw' => {`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam'`	`'global_param' => 'Localparam',`
	`'info' => 'Parameter',`
	`'content' => '',`
	`'type' => 'Fixed',`
	`'default' => '3'`
`},`	`},`
`'ram_CORE_NUM' => {`	`'ram_CORE_NUM' => {`
`'info' => 'Parameter',`
`'content' => '',`	`'content' => '',`
`'redefine_param' => 1,`	`'info' => 'Parameter',`
`'global_param' => 'Localparam',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => 'CORE_ID'`	`'default' => 'CORE_ID',`
	`'redefine_param' => 1,`
	`'global_param' => 'Localparam'`
	`}`
`},`	`},`
`'ram_FPGA_VENDOR' => {`	`'module_name' => 'wb_single_port_ram',`
`'content' => '"ALTERA","XILINX","GENERIC"',`	`'category' => 'RAM',`
`'info' => '',`	`'instance' => 'ram',`
`'default' => '"ALTERA"',`	`'module' => 'single_port_ram',`
`'type' => 'Combo-box',`	`'ports' => {`
`'global_param' => 'Localparam',`	`'ram_wb_to_jtag' => {`
`'redefine_param' => 1`	`'intfc_port' => 'jwb_o',`
	`'type' => 'output',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'range' => 'ram_WB2Jw-1 : 0'`
	`},`
	`'ram_jtag_to_wb' => {`
	`'intfc_port' => 'jwb_i',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'type' => 'input',`
	`'range' => 'ram_J2WBw-1 : 0'`
	`}`
`}`	`}`
`},`	`},`
	`'ProNoC_jtag_uart0' => {`
`'parameters' => {`	`'parameters' => {`
`'ram_JDw' => {`	`'uart_J2WBw' => {`
`'default' => 'ram_Dw',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'redefine_param' => 1,`	`'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',`
`'global_param' => 'Parameter',`
`'content' => '',`	`'content' => '',`
`'info' => 'Parameter'`	`'info' => undef,`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1`
`},`	`},`
`'ram_JTAG_CHAIN' => {`	`'uart_JTAG_CONNECT' => {`
`'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:`	`'redefine_param' => 1,`
`4: JTAG runtime memory programmers.`
`3: UART`
`1,2: reserved',`
`'content' => '1,2,3,4',`
`'redefine_param' => 0,`
`'global_param' => 'Parameter',`	`'global_param' => 'Parameter',`
`'default' => '4',`	`'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',`
	`'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.`

	`For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',`
	`'default' => '"ALTERA_JTAG_WB"',`
`'type' => 'Combo-box'`	`'type' => 'Combo-box'`
`},`	`},`
`'ram_JAw' => {`	`'uart_JINDEXw' => {`
`'info' => 'Parameter',`	`'type' => 'Fixed',`
	`'default' => '8',`
`'content' => '',`	`'content' => '',`
`'redefine_param' => 1,`	`'info' => 'Parameter',`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1`
	`},`
	`'uart_JSTATUSw' => {`
`'global_param' => 'Parameter',`	`'global_param' => 'Parameter',`
	`'redefine_param' => 1,`
	`'default' => '8',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '32'`	`'content' => '',`
	`'info' => 'Parameter'`
`},`	`},`
`'ram_JTAG_CONNECT' => {`	`'uart_JTAG_INDEX' => {`
`'type' => 'Combo-box',`
`'default' => '"ALTERA_JTAG_WB"',`
`'global_param' => 'Parameter',`	`'global_param' => 'Parameter',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',`	`'type' => 'Entry',`
`'info' => 'JTAG_CONNECT:`	`'default' => '126-CORE_ID',`
`if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '`	`'content' => '',`
	`'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.'`
`},`	`},`
`'ram_Dw' => {`	`'uart_JAw' => {`
`'content' => '8,1024,1',`	`'global_param' => 'Parameter',`
`'info' => 'Memory data width in Bits.',`
`'default' => '32',`
`'type' => 'Spin-button',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter'`	`'default' => '32',`
	`'type' => 'Fixed',`
	`'content' => '',`
	`'info' => 'Parameter'`
`},`	`},`
`'ram_JTAG_INDEX' => {`	`'uart_JDw' => {`
	`'type' => 'Fixed',`
	`'default' => '32',`
`'content' => '',`	`'content' => '',`
`'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.`	`'info' => 'Parameter',`
	`'global_param' => 'Parameter',`
`In case you have \'n\' memory in each processing core you can define their index as "nCORE_ID+1 , nCORE_ID+2 ...n*CORE_ID+n-1).`	`'redefine_param' => 1`
	`},`
`You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).`	`'uart_JTAG_CHAIN' => {`
	`'content' => '1,2,3,4',`
`',`	`'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:`
`'default' => 'CORE_ID',`	`4: JTAG runtime memory programmers.`
`'type' => 'Entry',`	`3: UART`
`'redefine_param' => 1,`	`1,2: reserved',`
	`'default' => '3',`
	`'type' => 'Combo-box',`
	`'redefine_param' => 0,`
`'global_param' => 'Parameter'`	`'global_param' => 'Parameter'`
`},`	`},`
`'ram_JINDEXw' => {`	`'uart_WB2Jw' => {`
	`'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',`
	`'type' => 'Fixed',`
`'content' => '',`	`'content' => '',`
	`'info' => '',`
	`'global_param' => 'Parameter',`
	`'redefine_param' => 1`
	`}`
	`},`
	`'localparam' => {`
	`'uart_Aw' => {`
`'info' => 'Parameter',`	`'info' => 'Parameter',`
	`'content' => '',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'default' => '8',`	`'default' => '1',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter'`	`'global_param' => 'Localparam'`
`},`	`},`
`'ram_JSTATUSw' => {`	`'uart_Dw' => {`
	`'global_param' => 'Localparam',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter',`	`'default' => '32',`
`'default' => '8',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'info' => 'Parameter',`	`'info' => 'Parameter',`
`'content' => ''`	`'content' => ''`
`},`	`},`
`'ram_WB2Jw' => {`	`'uart_BUFF_Aw' => {`
`'global_param' => 'Parameter',`	`'default' => '4',`
`'redefine_param' => 1,`	`'type' => 'Spin-button',`
`'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',`	`'content' => '2,16,1',`
	`'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',`
	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
	`},`
	`'uart_TAGw' => {`
	`'info' => 'Parameter',`
	`'content' => '',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'info' => undef,`	`'default' => '3',`
`'content' => ''`	`'redefine_param' => 1,`
	`'global_param' => 'Localparam'`
`},`	`},`
`'ram_J2WBw' => {`	`'uart_SELw' => {`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Parameter',`	`'global_param' => 'Localparam',`
`'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',`	`'content' => '',`
	`'info' => 'Parameter',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'info' => undef,`	`'default' => '4'`
`'content' => ''`
`}`	`}`
`},`	`},`
`'module' => 'single_port_ram',`	`'module_name' => 'pronoc_jtag_uart',`
`'module_name' => 'wb_single_port_ram',`	`'category' => 'Communication',`
`'ports' => {`	`'ports' => {`
`'ram_wb_to_jtag' => {`	`'uart_jtag_to_wb' => {`
	`'intfc_port' => 'jwb_i',`
	`'type' => 'input',`
	`'intfc_name' => 'socket:jtag_to_wb[0]',`
	`'range' => 'uart_J2WBw-1 : 0'`
	`},`
	`'uart_RxD_wr_sim' => {`
	`'range' => '',`
	`'type' => 'input',`
	`'intfc_port' => 'RxD_wr_sim',`
	`'intfc_name' => 'socket:RxD_sim[0]'`
	`},`
	`'uart_RxD_din_sim' => {`
	`'intfc_name' => 'socket:RxD_sim[0]',`
	`'intfc_port' => 'RxD_din_sim',`
	`'type' => 'input',`
	`'range' => '7:0 '`
	`},`
	`'uart_RxD_ready_sim' => {`
	`'intfc_port' => 'RxD_ready_sim',`
	`'intfc_name' => 'socket:RxD_sim[0]',`
`'type' => 'output',`	`'type' => 'output',`
	`'range' => ''`
	`},`
	`'uart_wb_to_jtag' => {`
`'intfc_port' => 'jwb_o',`	`'intfc_port' => 'jwb_o',`
`'intfc_name' => 'socket:jtag_to_wb[0]',`	`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'ram_WB2Jw-1 : 0'`	`'type' => 'output',`
`},`	`'range' => 'uart_WB2Jw-1 : 0'`
`'ram_jtag_to_wb' => {`
`'type' => 'input',`
`'intfc_port' => 'jwb_i',`
`'range' => 'ram_J2WBw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]'`
`}`	`}`
`},`	`},`
`'instance' => 'ram'`	`'module' => 'ProNoC_jtag_uart',`
	`'instance' => 'uart'`
`},`	`},`
`'mor1kx0' => {`	`'mor1kx0' => {`
`'module' => 'mor1kx',`
`'localparam' => {`	`'localparam' => {`
`'cpu_FEATURE_DIVIDER' => {`	`'cpu_FEATURE_INSTRUCTIONCACHE' => {`
`'default' => '"SERIAL"',`
`'type' => 'Combo-box',`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'content' => '"SERIAL","NONE"',`	`'content' => '"NONE","ENABLED"',`
`'info' => 'Specify the divider implementation'`	`'info' => '',`
	`'default' => '"ENABLED"',`
	`'type' => 'Combo-box'`
`},`	`},`
`'cpu_IRQ_NUM' => {`	`'cpu_IRQ_NUM' => {`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'default' => '32',`	`'default' => '32',`
`'type' => 'Fixed',`	`'type' => 'Fixed',`
`'info' => undef,`	`'info' => undef,`
`'content' => ''`	`'content' => '',`
`},`
`'cpu_FEATURE_IMMU' => {`
`'info' => '',`
`'content' => '"NONE","ENABLED"',`
`'redefine_param' => 1,`
`'global_param' => 'Localparam',`
`'default' => '"ENABLED"',`
`'type' => 'Combo-box'`
`},`
`'cpu_FEATURE_DATACACHE' => {`
`'content' => '"NONE","ENABLED"',`
`'info' => '',`
`'default' => '"ENABLED"',`
`'type' => 'Combo-box',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1`	`'redefine_param' => 1`
`},`	`},`
`'cpu_FEATURE_INSTRUCTIONCACHE' => {`	`'cpu_FEATURE_DATACACHE' => {`
`'info' => '',`	`'info' => '',`
`'content' => '"NONE","ENABLED"',`	`'content' => '"NONE","ENABLED"',`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'default' => '"ENABLED"',`
`'type' => 'Combo-box'`
`},`
`'cpu_FEATURE_DMMU' => {`
`'global_param' => 'Localparam',`
`'redefine_param' => 1,`
`'default' => '"ENABLED"',`	`'default' => '"ENABLED"',`
`'type' => 'Combo-box',`	`'type' => 'Combo-box',`
`'info' => '',`	`'redefine_param' => 1,`
`'content' => '"NONE","ENABLED"'`	`'global_param' => 'Localparam'`
`},`	`},`
`'cpu_OPTION_SHIFTER' => {`	`'cpu_OPTION_SHIFTER' => {`
`'content' => '"BARREL","SERIAL"',`
`'info' => 'Specify the shifter implementation',`
`'type' => 'Combo-box',`	`'type' => 'Combo-box',`
`'default' => '"BARREL"',`	`'default' => '"BARREL"',`
	`'info' => 'Specify the shifter implementation',`
	`'content' => '"BARREL","SERIAL"',`
	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
	`},`
	`'cpu_OPTION_OPERAND_WIDTH' => {`
	`'default' => '32',`
	`'type' => 'Fixed',`
	`'content' => '',`
	`'info' => 'Parameter',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1`	`'redefine_param' => 1`
`},`	`},`
`'cpu_FEATURE_MULTIPLIER' => {`	`'cpu_FEATURE_MULTIPLIER' => {`
`'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',`
`'info' => 'Specify the multiplier implementation',`
`'type' => 'Combo-box',`	`'type' => 'Combo-box',`
`'default' => '"THREESTAGE"',`	`'default' => '"THREESTAGE"',`
	`'info' => 'Specify the multiplier implementation',`
	`'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'redefine_param' => 1`	`'redefine_param' => 1`
`},`	`},`
`'cpu_OPTION_OPERAND_WIDTH' => {`	`'cpu_OPTION_DCACHE_SNOOP' => {`
	`'type' => 'Combo-box',`
	`'default' => '"ENABLED"',`
	`'info' => '',`
	`'content' => '"NONE","ENABLED"',`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
	`'redefine_param' => 1`
	`},`
	`'cpu_FEATURE_DMMU' => {`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'default' => '32',`	`'global_param' => 'Localparam',`
`'type' => 'Fixed',`	`'content' => '"NONE","ENABLED"',`
`'info' => 'Parameter',`	`'info' => '',`
`'content' => ''`	`'type' => 'Combo-box',`
	`'default' => '"ENABLED"'`
`},`	`},`
`'cpu_OPTION_DCACHE_SNOOP' => {`	`'cpu_FEATURE_DIVIDER' => {`
`'redefine_param' => 1,`	`'redefine_param' => 1,`
`'global_param' => 'Localparam',`	`'global_param' => 'Localparam',`
`'default' => '"ENABLED"',`	`'info' => 'Specify the divider implementation',`
	`'content' => '"SERIAL","NONE"',`
	`'default' => '"SERIAL"',`
	`'type' => 'Combo-box'`
	`},`
	`'cpu_FEATURE_IMMU' => {`
	`'global_param' => 'Localparam',`
	`'redefine_param' => 1,`
`'type' => 'Combo-box',`	`'type' => 'Combo-box',`
`'info' => '',`	`'default' => '"ENABLED"',`
`'content' => '"NONE","ENABLED"'`	`'content' => '"NONE","ENABLED"',`
	`'info' => ''`
`}`	`}`
`},`	`},`
	`'module_name' => 'mor1k',`
`'category' => 'Processor',`	`'category' => 'Processor',`
`'ports' => {`	`'ports' => {`
`'cpu_cpu_en' => {`	`'cpu_cpu_en' => {`
`'range' => '',`
`'intfc_name' => 'plug:enable[0]',`
`'intfc_port' => 'enable_i',`	`'intfc_port' => 'enable_i',`
`'type' => 'input'`
`}`
`},`
`'instance' => 'cpu',`
`'module_name' => 'mor1k'`
`}`
`},`
`'ports' => {`
`'source_clk_in' => {`
`'range' => '',`
`'intfc_name' => 'plug:clk[0]',`
`'instance_name' => 'clk_source0',`
`'type' => 'input',`
`'intfc_port' => 'clk_i'`
`},`
`'ram_wb_to_jtag' => {`
`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'ram_WB2Jw-1 : 0',`
`'type' => 'output',`
`'instance_name' => 'single_port_ram0',`
`'intfc_port' => 'jwb_o'`
`},`
`'uart_RxD_din_sim' => {`
`'intfc_port' => 'RxD_din_sim',`
`'instance_name' => 'ProNoC_jtag_uart0',`
`'type' => 'input',`
`'intfc_name' => 'socket:RxD_sim[0]',`
`'range' => '7:0 '`
`},`
`'source_reset_in' => {`
`'intfc_name' => 'plug:reset[0]',`
`'range' => '',`
`'intfc_port' => 'reset_i',`
`'instance_name' => 'clk_source0',`
`'type' => 'input'`
`},`
`'uart_jtag_to_wb' => {`
`'intfc_name' => 'socket:jtag_to_wb[0]',`
`'range' => 'uart_J2WBw-1 : 0',`
`'intfc_port' => 'jwb_i',`
`'instance_name' => 'ProNoC_jtag_uart0',`
`'type' => 'input'`
`},`
`'uart_RxD_ready_sim' => {`
`'intfc_name' => 'socket:RxD_sim[0]',`
`'range' => '',`
`'instance_name' => 'ProNoC_jtag_uart0',`
`'type' => 'output',`
`'intfc_port' => 'RxD_ready_sim'`
`},`
`'ni_current_e_addr' => {`
`'intfc_name' => 'socket:ni[0]',`
`'range' => 'ni_EAw-1 : 0',`
`'instance_name' => 'ni_master0',`
`'type' => 'input',`
`'intfc_port' => 'current_e_addr'`
`},`
`'ni_chan_in' => {`
`'instance_name' => 'ni_master0',`
`'intfc_port' => 'chan_in',`
`'type' => 'input',`
`'intfc_name' => 'socket:ni[0]',`
`'range' => 'smartflit_chanel_t'`
`},`
`'ni_chan_out' => {`
`'instance_name' => 'ni_master0',`
`'type' => 'output',`
`'intfc_port' => 'chan_out',`
`'intfc_name' => 'socket:ni[0]',`
`'range' => 'smartflit_chanel_t'`
`},`
`'ni_current_r_addr' => {`
`'range' => 'ni_RAw-1 : 0',`
`'intfc_name' => 'socket:ni[0]',`
`'instance_name' => 'ni_master0',`
`'intfc_port' => 'current_r_addr',`
`'type' => 'input'`
`},`
`'uart_RxD_wr_sim' => {`
`'range' => '',`
`'intfc_name' => 'socket:RxD_sim[0]',`
`'type' => 'input',`	`'type' => 'input',`
`'instance_name' => 'ProNoC_jtag_uart0',`
`'intfc_port' => 'RxD_wr_sim'`
`},`
`'uart_wb_to_jtag' => {`
`'intfc_port' => 'jwb_o',`
`'instance_name' => 'ProNoC_jtag_uart0',`
`'type' => 'output',`
`'range' => 'uart_WB2Jw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]'`
`},`
`'cpu_cpu_en' => {`
`'intfc_name' => 'plug:enable[0]',`	`'intfc_name' => 'plug:enable[0]',`
`'range' => '',`	`'range' => ''`
`'instance_name' => 'mor1kx0',`	`}`
`'intfc_port' => 'enable_i',`
`'type' => 'input'`
`},`	`},`
`'ram_jtag_to_wb' => {`	`'module' => 'mor1kx',`
`'intfc_port' => 'jwb_i',`	`'instance' => 'cpu'`
`'instance_name' => 'single_port_ram0',`
`'type' => 'input',`
`'range' => 'ram_J2WBw-1 : 0',`
`'intfc_name' => 'socket:jtag_to_wb[0]'`
`}`	`}`
`}`	`}`
`}, 'ip_gen' ),`	`}, 'ip_gen' ),`
`'modules' => {},`	`'JTAG' => {`
`'ROM0' => {`	`'M_CHAIN' => '0'`
`'start' => 0,`
`'end' => 49152`
`},`
`'device_win_adj' => {`
`'ha' => '0',`
`'va' => '0'`
`},`
`'global_param' => {`
`'CORE_ID' => 3,`
`'SW_LOC' => '/home/alireza/work/git/hca_git/mpsoc_work/SOC/mor1k_tile/sw'`
`},`
`'clk_source0' => {`
`'version' => 1`
`},`
`'graph_save' => {},`
`'mor1kx0' => {`
`'version' => 26`
`},`
`'single_port_ram0' => {`
`'version' => 39`
`},`
`'soc_name' => 'mor1k_tile',`
`'tile_diagram' => {`
`'show_clk' => 0,`
`'show_reset' => 0,`
`'show_unused' => 1`
`},`	`},`
`'noc_param' => {},`
`'hdl_files_ticked' => undef,`
`'parameters_order' => {`	`'parameters_order' => {`
`'current_module_param' => [`	`'current_module_param' => [`
`'FPGA_VENDOR',`	`'FPGA_VENDOR',`
`'M',`	`'M',`
`'S',`	`'S',`
Line 2392...	Line 2431...
`'PRESCALER_WIDTH',`	`'PRESCALER_WIDTH',`
`'BUFF_Aw',`	`'BUFF_Aw',`
`'INCLUDE_SIM_PRINTF'`	`'INCLUDE_SIM_PRINTF'`
`]`	`]`
`},`	`},`
`'JTAG' => {`	`'hdl_files' => undef`
`'M_CHAIN' => '0'`
`},`
`'MEM0' => {`
`'percent' => 75,`
`'width' => '14'`
`},`
`'ProNoC_jtag_uart0' => {`
`'version' => 11`
`},`
`'Unset-intfc' => {},`
`'RAM0' => {`
`'end' => 65536,`
`'start' => 49152`
`},`
`'ni_master0' => {`
`'version' => 84`
`}`
`}, 'soc' );`	`}, 'soc' );`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [soc/] [mor1k_tile.SOC] - Diff between revs 54 and 56