URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [verilog/] [functions.v] - Diff between revs 48 and 56

Rev 48	Rev 56
Line 1...	Line 1...

`function integer log2;`
`input integer number; begin`
`log2=0;`
`while(2**log2<number) begin`
`log2=log2+1;`
`end`
`end`
`endfunction // log2`

`function [15:0]i2s;`	`function [15:0]i2s;`
`input integer c; integer i; integer tmp; begin`	`input integer c; integer i; integer tmp; begin`
`tmp =0;`	`tmp =0;`
`for (i=0; i<2; i=i+1) begin`	`for (i=0; i<2; i=i+1) begin`
Line 18...	Line 11...
`i2s = tmp[15:0];`	`i2s = tmp[15:0];`
`end`	`end`
`endfunction //i2s`	`endfunction //i2s`

`/*`	`/*`

	`function integer log2;`
	`input integer number; begin`
	`log2=0;`
	`while(2**log2<number) begin`
	`log2=log2+1;`
	`end`
	`end`
	`endfunction // log2`

`function [159:0]f2s;`	`function [159:0]f2s;`
`input real f; reg s;reg b; integer i; integer j;integer a; real tmp; begin`	`input real f; reg s;reg b; integer i; integer j;integer a; real tmp; begin`
`s=0;`	`s=0;`
`b=0;`	`b=0;`
`f2s={160{1'b0}};`	`f2s={160{1'b0}};`