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`timescale 1ns/1ps
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`include "pronoc_def.v"
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/****************************
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/****************************
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* This module can inject and eject packets from the NoC.
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* This module can inject and eject packets from the NoC.
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* It can be used in simulation for injecting real application traces to the NoC
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* It can be used in simulation for injecting real application traces to the NoC
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* *************************/
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* *************************/
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module multicast_injector
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module multicast_injector #(
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import pronoc_pkg::*;
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parameter NOC_ID=0
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(
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)(
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//general
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//general
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current_e_addr,
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current_e_addr,
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reset,
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reset,
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clk,
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clk,
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//noc port
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//noc port
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Line 19... |
//control interafce
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//control interafce
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pck_injct_in,
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pck_injct_in,
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pck_injct_out
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pck_injct_out
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);
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);
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`NOC_CONF
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//general
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//general
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input reset,clk;
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input reset,clk;
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input [EAw-1 :0 ] current_e_addr;
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input [EAw-1 :0 ] current_e_addr;
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// the destination endpoint address
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// the destination endpoint address
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Line 40... |
wire [RAw-1 :0 ] current_r_addr;
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wire [RAw-1 :0 ] current_r_addr;
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wire [DSTPw-1 : 0 ] destport;
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wire [DSTPw-1 : 0 ] destport;
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reg flit_wr;
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reg flit_wr;
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assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
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assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
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/*
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/*
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conventional_routing #(
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conventional_routing #(
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.NOC_ID(NOC_ID),
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.TOPOLOGY(TOPOLOGY),
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.TOPOLOGY(TOPOLOGY),
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.ROUTE_NAME(ROUTE_NAME),
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.ROUTE_NAME(ROUTE_NAME),
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.ROUTE_TYPE(ROUTE_TYPE),
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.ROUTE_TYPE(ROUTE_TYPE),
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.T1(T1),
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.T1(T1),
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.T2(T2),
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.T2(T2),
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Line 70... |
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*/
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*/
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assign destport = 7;
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assign destport = 7;
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localparam
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localparam
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HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
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HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
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HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
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HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
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HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp;
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HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp;
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wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
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wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
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wire [Fw-1 : 0] hdr_flit_out;
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wire [Fw-1 : 0] hdr_flit_out;
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header_flit_generator #(
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header_flit_generator #(
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.NOC_ID(NOC_ID),
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.DATA_w(HDR_DATA_w)
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.DATA_w(HDR_DATA_w)
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)
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) the_header_flit_generator (
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the_header_flit_generator
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(
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.flit_out (hdr_flit_out),
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.flit_out (hdr_flit_out),
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.vc_num_in (pck_injct_in.vc),
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.vc_num_in (pck_injct_in.vc),
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.class_in (pck_injct_in.class_num),
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.class_in (pck_injct_in.class_num),
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.dest_e_addr_in (pck_injct_in.endp_addr),
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.dest_e_addr_in (pck_injct_in.endp_addr),
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.src_e_addr_in (current_e_addr),
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.src_e_addr_in (current_e_addr),
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Line 193... |
end
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end
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end
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end
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reg [V-1 : 0] credit_o;
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reg [V-1 : 0] credit_o;
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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if(reset) begin
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if(`pronoc_reset) begin
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flit_type<=HEADER;
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flit_type<=HEADER;
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counter<=0;
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counter<=0;
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counter2<=0;
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counter2<=0;
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credit_o<={V{1'b0}};
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credit_o<={V{1'b0}};
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end else begin
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end else begin
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Line 211... |
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injector_ovc_status #(
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multi_cast_injector_ovc_status #(
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.V(V),
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.V(V),
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.B(LB),
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.B(LB),
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.CRDTw(CRDTw)
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.CRDTw(CRDTw)
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)
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)
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the_ovc_status
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the_ovc_status
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Line 229... |
.clk(clk),
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.clk(clk),
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.reset(reset)
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.reset(reset)
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);
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);
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wire [HDR_DATA_w-1 : 0] hdr_data_o;
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wire [HDR_DATA_w-1 : 0] hdr_data_o;
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hdr_flit_t hdr_flit_i;
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hdr_flit_t hdr_flit_i;
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header_flit_info
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header_flit_info
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#(
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#(
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.NOC_ID (NOC_ID),
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.DATA_w (HDR_DATA_w )
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.DATA_w (HDR_DATA_w )
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) extractor (
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) extractor (
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.flit(chan_in.flit_chanel.flit),
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.flit(chan_in.flit_chanel.flit),
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.hdr_flit(hdr_flit_i),
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.hdr_flit(hdr_flit_i),
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.data_o(hdr_data_o)
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.data_o(hdr_data_o)
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Line 274... |
end//always
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end//always
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always_ff @(posedge clk or posedge reset) begin
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always_ff @(`pronoc_clk_reset_edge) begin
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if (reset) begin
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if (`pronoc_reset) begin
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rsv_counter[i]<= {PCK_SIZw{1'b0}};
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rsv_counter[i]<= {PCK_SIZw{1'b0}};
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h2t_counter[i]<= 16'd0;
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h2t_counter[i]<= 16'd0;
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sender_endp_addr_reg [i]<= {EAw{1'b0}};
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sender_endp_addr_reg [i]<= {EAw{1'b0}};
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end else begin
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end else begin
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h2t_counter[i]<=h2t_counter_next[i];
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h2t_counter[i]<=h2t_counter_next[i];
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Line 302... |
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for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
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for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
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always_ff @(posedge clk or posedge reset) begin
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always_ff @(`pronoc_clk_reset_edge) begin
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if (reset) begin
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if (`pronoc_reset) begin
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pck_data_o_gen [i][k] <= {Fpay{1'b0}};
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pck_data_o_gen [i][k] <= {Fpay{1'b0}};
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end else begin
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end else begin
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if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
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if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
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if (chan_in.flit_chanel.flit.hdr_flag )begin
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if (chan_in.flit_chanel.flit.hdr_flag )begin
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Line 451... |
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/******************
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/******************
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* ovc_status
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* ovc_status
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*******************/
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*******************/
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module injector_ovc_status #(
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module multi_cast_injector_ovc_status #(
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parameter V = 4,
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parameter V = 4,
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parameter B = 16,
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parameter B = 16,
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parameter CRDTw =4
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parameter CRDTw =4
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)
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)
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(
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(
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Line 489... |
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genvar i;
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genvar i;
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generate
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generate
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for(i=0;i
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for(i=0;i
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`ifdef SYNC_RESET_MODE
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always @ (`pronoc_clk_reset_edge)begin
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always @ (posedge clk )begin
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if(`pronoc_reset)begin
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`else
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always @ (posedge clk or posedge reset)begin
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`endif
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if(reset)begin
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credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
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credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
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end else begin
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end else begin
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if( wr_in[i] && ~credit_in[i]) credit[i] <= credit[i]-1'b1;
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if( wr_in[i] && ~credit_in[i]) credit[i] <= credit[i]-1'b1;
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if( ~wr_in[i] && credit_in[i]) credit[i] <= credit[i]+1'b1;
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if( ~wr_in[i] && credit_in[i]) credit[i] <= credit[i]+1'b1;
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end //reset
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end //reset
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Line 504... |
assign nearly_full_vc[i]= (credit[i] == 1) | full_vc[i];
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assign nearly_full_vc[i]= (credit[i] == 1) | full_vc[i];
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assign empty_vc[i] = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
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assign empty_vc[i] = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
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end//for
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end//for
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endgenerate
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endgenerate
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endmodule
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endmodule
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/**************************************
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*
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*
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* ***********************************/
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module packet_injector_verilator
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import pronoc_pkg::*;
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(
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//general
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current_e_addr,
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reset,
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clk,
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//noc port
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chan_in,
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chan_out,
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//control interafce
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pck_injct_in_data,
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pck_injct_in_size,
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pck_injct_in_endp_addr,
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pck_injct_in_class_num,
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pck_injct_in_init_weight,
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pck_injct_in_vc,
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pck_injct_in_pck_wr,
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pck_injct_in_ready,
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pck_injct_out_data,
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pck_injct_out_size,
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pck_injct_out_endp_addr,
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pck_injct_out_class_num,
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pck_injct_out_init_weight,
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pck_injct_out_vc,
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pck_injct_out_pck_wr,
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pck_injct_out_ready,
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pck_injct_out_distance,
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pck_injct_out_h2t_delay,
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min_pck_size
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);
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//general
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input reset,clk;
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input [EAw-1 :0 ] current_e_addr;
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// the destination endpoint address
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//NoC interface
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input smartflit_chanel_t chan_in;
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output smartflit_chanel_t chan_out;
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//control interafce
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input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;
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input [PCK_SIZw-1 : 0] pck_injct_in_size;
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input [EAw-1 : 0] pck_injct_in_endp_addr;
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input [Cw-1 : 0] pck_injct_in_class_num;
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input [WEIGHTw-1 : 0] pck_injct_in_init_weight;
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input [V-1 : 0] pck_injct_in_vc;
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input pck_injct_in_pck_wr;
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input [V-1 : 0] pck_injct_in_ready;
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output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;
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output [PCK_SIZw-1 : 0] pck_injct_out_size;
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output [EAw-1 : 0] pck_injct_out_endp_addr;
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output [Cw-1 : 0] pck_injct_out_class_num;
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output [WEIGHTw-1 : 0] pck_injct_out_init_weight;
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output [V-1 : 0] pck_injct_out_vc;
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output pck_injct_out_pck_wr;
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output [V-1 : 0] pck_injct_out_ready;
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output [DISTw-1 : 0] pck_injct_out_distance;
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output [15 : 0] pck_injct_out_h2t_delay;
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output [4 : 0] min_pck_size;
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pck_injct_t pck_injct_in;
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pck_injct_t pck_injct_out;
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assign pck_injct_in.data = pck_injct_in_data;
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assign pck_injct_in.size = pck_injct_in_size;
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assign pck_injct_in.endp_addr = pck_injct_in_endp_addr;
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assign pck_injct_in.class_num = pck_injct_in_class_num;
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assign pck_injct_in.init_weight = pck_injct_in_init_weight;
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assign pck_injct_in.vc = pck_injct_in_vc;
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assign pck_injct_in.pck_wr = pck_injct_in_pck_wr;
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assign pck_injct_in.ready = pck_injct_in_ready;
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assign pck_injct_out_data = pck_injct_out.data;
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assign pck_injct_out_size = pck_injct_out.size;
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assign pck_injct_out_endp_addr = pck_injct_out.endp_addr;
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assign pck_injct_out_class_num = pck_injct_out.class_num;
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assign pck_injct_out_init_weight = pck_injct_out.init_weight;
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assign pck_injct_out_vc = pck_injct_out.vc;
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assign pck_injct_out_pck_wr = pck_injct_out.pck_wr;
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assign pck_injct_out_ready = pck_injct_out.ready;
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assign pck_injct_out_distance = pck_injct_out.distance;
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assign pck_injct_out_h2t_delay = pck_injct_out.h2t_delay;
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packet_injector injector (
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.current_e_addr (current_e_addr ),
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.reset (reset ),
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.clk (clk ),
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.chan_in (chan_in ),
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.chan_out (chan_out ),
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.pck_injct_in (pck_injct_in ),
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.pck_injct_out (pck_injct_out ));
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localparam
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HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
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HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
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HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp,
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REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,
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REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
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REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
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REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
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CNTw = log2(REMAIN_DAT_FLIT),
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MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
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assign min_pck_size = MIN_PCK_SIZ[4:0];
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// `ifdef VERILATOR
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// logic endp_is_active /*verilator public_flat_rd*/ ;
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//
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// always @ (*) begin
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// endp_is_active = 1'b0;
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// if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
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// if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
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// if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
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// end
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// `endif
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endmodule
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