OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_modelsim/] [pck_injector_test.sv] - Diff between revs 54 and 56

Show entire file | Details | Blame | View Log

Rev 54 Rev 56
Line 1... Line 1... 
// synthesis translate_off
 
// synthesis translate_off
 
`timescale   1ns/1ns
 
`include "pronoc_def.v"
 
 
 
 
 
 
 
 
 
module pck_injector_test;
 
module pck_injector_test;
 
 
 
        parameter NOC_ID=0;
 
        import pronoc_pkg::*;
 
    `NOC_CONF
 
 
 
 
 
        reg     reset ,clk;
 
        reg     reset ,clk;
 
 
 
 
 
        initial begin
 
        initial begin
 
                clk = 1'b0;
 
                clk = 1'b0;
 
                forever clk = #10 ~clk;
 
                forever clk = #10 ~clk;
 
        end
 
        end
 
 
 
 
 
 
 
 
 
        smartflit_chanel_t chan_in_all  [NE-1 : 0];
 
        smartflit_chanel_t chan_in_all  [NE-1 : 0];
 
        smartflit_chanel_t chan_out_all [NE-1 : 0];
 
        smartflit_chanel_t chan_out_all [NE-1 : 0];
 
 
 
 
 
        pck_injct_t pck_injct_in [NE-1 : 0];
 
        pck_injct_t pck_injct_in [NE-1 : 0];
 
        pck_injct_t pck_injct_out[NE-1 : 0];
 
        pck_injct_t pck_injct_out[NE-1 : 0];
 
 
 
 
 
 
 
 
 
        noc_top         the_noc
 
        noc_top  # (
 
        (
 
                .NOC_ID(NOC_ID)
 
 
 
        ) the_noc (
 
                .reset(reset),
 
                .reset(reset),
 
                .clk(clk),
 
                .clk(clk),
 
                .chan_in_all(chan_in_all),
 
                .chan_in_all(chan_in_all),
 
                .chan_out_all(chan_out_all),
 
                .chan_out_all(chan_out_all),
 
                .router_event( )
 
                .router_event( )
 
        );
 
        );
 
 
 
 
 
        reg [NEw-1 : 0] dest_id [NE-1 : 0];
 
        reg [NEw-1 : 0] dest_id [NE-1 : 0];
 
 
 
        wire [NEw-1 : 0] src_id  [NE-1 : 0];
 
        wire [NEw-1: 0] current_e_addr [NE-1 : 0];
 
        wire [NEw-1: 0] current_e_addr [NE-1 : 0];
 
 
 
 
 
        genvar i;
 
        genvar i;
 
        generate
 
        generate
 
        for(i=0; i< NE; i=i+1) begin : endpoints
 
        for(i=0; i< NE; i=i+1) begin : endpoints
 
 
 
 
 
                endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode1 ( .id(i[NEw-1 :0]), .code(current_e_addr[i]));
 
                endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode1 ( .id(i[NEw-1 :0]), .code(current_e_addr[i]));
 
 
 
 
 
                packet_injector pck_inj(
 
                packet_injector #(
 
 
 
                        .NOC_ID(NOC_ID)
 
 
 
                ) pck_inj (
 
                        //general
 
                        //general
 
                        .current_e_addr(current_e_addr[i]),
 
                        .current_e_addr(current_e_addr[i]),
 
                        .reset(reset),
 
                        .reset(reset),
 
                        .clk(clk),
 
                        .clk(clk),
 
                        //noc port
 
                        //noc port
Line 57... Line 59... 
 
 
 
 
 
 
 
 
           reg [31:0]k;
 
           reg [31:0]k;
 
 
 
 
 
                initial begin
 
                initial begin
 
 
 
`ifdef ACTIVE_LOW_RESET_MODE
 
 
 
        reset = 1'b0;
 
 
 
 `else
 
                        reset = 1'b1;
 
                        reset = 1'b1;
 
 
 
`endif
 
                        k=0;
 
                        k=0;
 
                        pck_injct_in[i].data =0;
 
                        pck_injct_in[i].data =0;
 
                        #10
 
                        #10
 
                        pck_injct_in[i].class_num=0;
 
                        pck_injct_in[i].class_num=0;
 
                        pck_injct_in[i].init_weight=1;
 
                        pck_injct_in[i].init_weight=1;
 
                        pck_injct_in[i].vc=1;
 
                        pck_injct_in[i].vc=1;
 
                        pck_injct_in[i].pck_wr=1'b0;
 
                        pck_injct_in[i].pck_wr=1'b0;
 
                        #100
 
                        #100
 
                        @(posedge clk) #1;
 
                        @(posedge clk) #1;
 
                        reset=1'b0;
 
                        reset=~reset;
 
                        #100
 
                        #100
 
                        @(posedge clk) #1;
 
                        @(posedge clk) #1;
 
                        if(i==1) begin
 
                        if(i==1) begin
 
                                repeat(10) begin
 
                                repeat(10) begin
 
                                        while (pck_injct_out[i].ready[0] == 1'b0) @(posedge clk)   #1;
 
                                        while (pck_injct_out[i].ready[0] == 1'b0) @(posedge clk)   #1;
Line 96... Line 102... 
 
 
 
 
 
 
 
 
 
 
 
 
                end
 
                end
 
 
 
 
 
 
 
                endp_addr_decoder  #(   .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) decode1 ( .id(src_id[i]), .code(pck_injct_out[i].endp_addr));
 
 
 
 
 
                always @(posedge clk) begin
 
                always @(posedge clk) begin
 
                        if(pck_injct_out[i].pck_wr) begin
 
                        if(pck_injct_out[i].pck_wr) begin
 
                                $display ("%t:pck_inj(%d) got a packet: source=%d, size=%d, data=%h",$time,i,
 
                                $display ("%t:pck_inj(%d) got a packet from source_id=%d, with size=%d flits and data=%h",$time,i,
 
                                                pck_injct_out[i].endp_addr,pck_injct_out[i].size,pck_injct_out[i].data);
 
                                                src_id[i],pck_injct_out[i].size,pck_injct_out[i].data);
 
                        end
 
                        end
 
 
 
 
 
                end
 
                end
 
 
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.