Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

    localparam

    localparam

      NX = T1,

      NX = T1,

      NY = T2,

      NY = T2,

      RXw = log2(NX),    // number of node in x axis

      RXw = log2(NX),    // number of node in x axis

      EXw = log2(NX),    // number of node in x axis

      EXw = log2(NX),    // number of node in x axis

    wire [RXw-1 : 0] current_x;

    wire [RXw-1 : 0] current_x;

    wire [EXw-1 : 0] x_dst_in,x_src_in;

    wire [EXw-1 : 0] x_dst_in,x_src_in;

    wire [RYw-1 : 0] current_y;

    wire [RYw-1 : 0] current_y;

/*******************

/*******************

 *

 *

 * *****************/

 * *****************/

 module check_destination_addr #(

 module check_destination_addr #(

    parameter TOPOLOGY = "MESH",

    parameter TOPOLOGY = "MESH",

    parameter T1=2,

    parameter T1=2,

    parameter T2=2,

    parameter T2=2,

    parameter T3=2,

    parameter T3=2,

    parameter T4=2,

    parameter T4=2,

    generate

    generate

    if(CAST_TYPE != "UNICAST") begin

    if(CAST_TYPE != "UNICAST") begin

            wire [NE-1 : 0] dest_mcast_all_endp;

            wire [NE-1 : 0] dest_mcast_all_endp;

                .dest_e_addr(dest_e_addr),

                .dest_e_addr(dest_e_addr),

                .dest_o(dest_mcast_all_endp),

                .dest_o(dest_mcast_all_endp),

                .row_has_any_dest( ),

                .row_has_any_dest( ),

                .is_unicast()

                .is_unicast()

            );

            );

            );

            );

    /* verilator lint_off WIDTH */

    /* verilator lint_off WIDTH */

    end else if  (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin :tori

    end else if  (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin :tori

    /* verilator lint_on WIDTH */

    /* verilator lint_on WIDTH */

        mesh_tori_addr_coder #(

        mesh_tori_addr_coder #(

            .NX    (T1   ),

            .NX    (T1   ),

            .NY    (T2   ),

            .NY    (T2   ),

            .NL    (T3   ),

            .NL    (T3   ),

            .NE    (NE   ),

            .NE    (NE   ),

            .EAw   (EAw  )

            .EAw   (EAw  )

    endgenerate

    endgenerate

endmodule

endmodule

module check_pck_size #(

module check_pck_size #(

    parameter V=2,

    parameter V=2,

    parameter MIN_PCK_SIZE=2,

    parameter MIN_PCK_SIZE=2,

    parameter Fw=36,

    parameter Fw=36,

    parameter DAw=4,

    parameter DAw=4,

    parameter CAST_TYPE="UNICAST",

    parameter CAST_TYPE="UNICAST",

    wire [V-1 : 0] vc_hdr_wr_en;

    wire [V-1 : 0] vc_hdr_wr_en;

    wire [V-1 : 0] onehot;

    wire [V-1 : 0] onehot;

    localparam MIN_B =  (B<LB)? B : LB;

    localparam MIN_B =  (B<LB)? B : LB;

   genvar i;

   genvar i;

   generate

   generate

   for (i=0;i<V;i=i+1) begin

   for (i=0;i<V;i=i+1) begin

        always @(*) begin

        always @(*) begin

                .ld     (vc_hdr_wr_en [i] ),

                .ld     (vc_hdr_wr_en [i] ),

                .out    (dest_e_addr[i])

                .out    (dest_e_addr[i])

            );

            );

                .dest_e_addr(dest_e_addr[i]),

                .dest_e_addr(dest_e_addr[i]),

                .dest_o(dest_mcast_all_endp[i]),

                .dest_o(dest_mcast_all_endp[i]),

                .row_has_any_dest(),

                .row_has_any_dest(),

                .is_unicast()

                .is_unicast()

            );

            );