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Line 26... |
**
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**
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**************************************************************/
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**************************************************************/
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module flit_buffer
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module flit_buffer
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import pronoc_pkg::*;
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#(
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#(
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parameter B =4,
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parameter B =4,
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parameter SSA_EN="YES" // "YES" , "NO"
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parameter SSA_EN="YES", // "YES" , "NO"
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parameter Fw=32,
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parameter PCK_TYPE ="MULTI_FLIT",
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parameter CAST_TYPE = "UNICAST",
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parameter DEBUG_EN = 1,
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parameter V=1
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)
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)
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(
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(
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din, // Data in
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din, // Data in
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vc_num_wr,//write virtual channel
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vc_num_wr,//write virtual channel
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vc_num_rd,//read virtual channel
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vc_num_rd,//read virtual channel
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Line 53... |
multiple_dest, // incr rd-sub
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multiple_dest, // incr rd-sub
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sub_rd_ptr_ld, // load rd_ptr to sub_rd_pt
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sub_rd_ptr_ld, // load rd_ptr to sub_rd_pt
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flit_is_tail
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flit_is_tail
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);
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);
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function integer log2;
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input integer number; begin
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log2=(number <=1) ? 1: 0;
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while(2**log2
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log2=log2+1;
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end
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end
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endfunction // log2
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localparam
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localparam
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Bw = (B==1)? 1 : log2(B),
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Bw = (B==1)? 1 : log2(B),
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BV = B * V,
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BV = B * V,
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Line 727... |
wire [DATA_WIDTH-1 : 0] mux_out;
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wire [DATA_WIDTH-1 : 0] mux_out;
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reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0];
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reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0];
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for(i=0;i
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for(i=0;i
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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//if (reset) begin
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//if (`pronoc_reset) begin
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// shiftreg[i] <= {MAX_DEPTH{1'b0}};
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// shiftreg[i] <= {MAX_DEPTH{1'b0}};
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//end else begin
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//end else begin
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if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH-3 : 0] ,din[i]};
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if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH-3 : 0] ,din[i]};
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//end
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//end
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end
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end
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Line 929... |
wire [DATA_WIDTH-1 : 0] mux_out;
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wire [DATA_WIDTH-1 : 0] mux_out;
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reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0];
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reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0];
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for(i=0;i
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for(i=0;i
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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//if (reset) begin
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//if (`pronoc_reset) begin
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// shiftreg[i] <= {MAX_DEPTH{1'b0}};
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// shiftreg[i] <= {MAX_DEPTH{1'b0}};
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//end else begin
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//end else begin
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if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH-3 : 0] ,din[i]};
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if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH-3 : 0] ,din[i]};
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//end
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//end
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end
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end
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Line 1020... |
//synthesis translate_off
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//synthesis translate_off
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//synopsys translate_off
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//synopsys translate_off
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if(~reset)begin
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if(`pronoc_reset==0)begin
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if (wr_en && ~rd_en && full) begin
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if (wr_en && ~rd_en && full) begin
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$display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
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$display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
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$finish;
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$finish;
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end
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end
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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Line 1043... |
//synopsys translate_on
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//synopsys translate_on
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//synthesis translate_on
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//synthesis translate_on
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endmodule
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endmodule
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/***************
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fwft_fifo_bram
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****************/
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module fwft_fifo_bram #(
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module fwft_fifo_bram #(
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parameter DATA_WIDTH = 2,
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parameter DATA_WIDTH = 2,
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parameter MAX_DEPTH = 2,
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parameter MAX_DEPTH = 2,
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parameter IGNORE_SAME_LOC_RD_WR_WARNING="YES" // "YES" , "NO"
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parameter IGNORE_SAME_LOC_RD_WR_WARNING="YES" // "YES" , "NO"
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| Line 1081... |
Line 1089... |
wire bram_empty, bram_rd_en, bram_wr_en;
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wire bram_empty, bram_rd_en, bram_wr_en;
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wire [DATA_WIDTH-1 : 0] bram_dout;
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wire [DATA_WIDTH-1 : 0] bram_dout;
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wire [DATA_WIDTH-1 : 0] out_reg;
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wire [DATA_WIDTH-1 : 0] out_reg;
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reg [DATA_WIDTH-1 : 0] out_reg_next;
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reg [DATA_WIDTH-1 : 0] out_reg_next;
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wire [DEPTH_DATA_WIDTH-1 : 0] depth;
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reg [DEPTH_DATA_WIDTH-1 : 0] depth_next;
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assign dout = (bram_out_is_valid)? bram_dout : out_reg;
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assign dout = (bram_out_is_valid)? bram_dout : out_reg;
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assign pass_din_to_out_reg = (wr_en & ~valid)| // a write has been recived while the reg_flit is not valid
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assign pass_din_to_out_reg = (wr_en & ~valid)| // a write has been recived while the reg_flit is not valid
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(wr_en & valid & bram_empty & rd_en); //or its valid but bram is empty and its got a read request
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(wr_en & valid & bram_empty & rd_en); //or its valid but bram is empty and its got a read request
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| Line 1098... |
Line 1109... |
assign bram_out_is_valid_next = (bram_rd_en )? (rd_en & ~bram_empty): 1'b0;
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assign bram_out_is_valid_next = (bram_rd_en )? (rd_en & ~bram_empty): 1'b0;
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always @(*) begin
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always @(*) begin
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valid_next = valid;
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valid_next = valid;
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if(out_reg_wr_en) valid_next =1'b1;
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if(depth_next == {DEPTH_DATA_WIDTH{1'b0}}) valid_next =1'b0;
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else if(out_reg_wr_en) valid_next =1'b1;
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else if( bram_empty & rd_en) valid_next =1'b0;
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else if( bram_empty & rd_en) valid_next =1'b0;
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end
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end
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bram_based_fifo #(
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bram_based_fifo #(
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| Line 1118... |
Line 1130... |
.empty(bram_empty),
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.empty(bram_empty),
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.reset(reset),
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.reset(reset),
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.clk(clk)
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.clk(clk)
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);
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);
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wire [DEPTH_DATA_WIDTH-1 : 0] depth;
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reg [DEPTH_DATA_WIDTH-1 : 0] depth_next;
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pronoc_register #(.W(DATA_WIDTH) ) reg1 (.in(out_reg_next ), .out(out_reg), .reset(reset), .clk(clk));
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pronoc_register #(.W(DATA_WIDTH) ) reg1 (.in(out_reg_next ), .out(out_reg), .reset(reset), .clk(clk));
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pronoc_register #(.W(1) ) reg2 (.in(valid_next ), .out(valid), .reset(reset), .clk(clk));
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pronoc_register #(.W(1) ) reg2 (.in(valid_next ), .out(valid), .reset(reset), .clk(clk));
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pronoc_register #(.W(1) ) reg3 (.in(bram_out_is_valid_next ), .out(bram_out_is_valid), .reset(reset), .clk(clk));
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pronoc_register #(.W(1) ) reg3 (.in(bram_out_is_valid_next ), .out(bram_out_is_valid), .reset(reset), .clk(clk));
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| Line 1135... |
Line 1146... |
out_reg_next = out_reg;
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out_reg_next = out_reg;
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depth_next = depth;
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depth_next = depth;
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if (wr_en & ~rd_en) depth_next = depth + 1'h1;
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if (wr_en & ~rd_en) depth_next = depth + 1'h1;
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else if (~wr_en & rd_en) depth_next = depth - 1'h1;
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else if (~wr_en & rd_en) depth_next = depth - 1'h1;
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if(pass_din_to_out_reg) out_reg_next = din;
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if(pass_din_to_out_reg) out_reg_next = din;
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if(bram_out_is_valid) out_reg_next = bram_dout;
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else if(bram_out_is_valid) out_reg_next = bram_dout;
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end
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end
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| Line 1254... |
Line 1265... |
dout <= queue[rd_ptr];
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dout <= queue[rd_ptr];
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (reset) begin
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if (`pronoc_reset) begin
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rd_ptr <= {Bw{1'b0}};
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rd_ptr <= {Bw{1'b0}};
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wr_ptr <= {Bw{1'b0}};
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wr_ptr <= {Bw{1'b0}};
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depth <= {DEPTHw{1'b0}};
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depth <= {DEPTHw{1'b0}};
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end
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end
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else begin
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else begin
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Line 1290... |
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//synthesis translate_off
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//synthesis translate_off
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//synopsys translate_off
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//synopsys translate_off
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if(~reset)begin
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if(`pronoc_reset==1'b0)begin
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if (wr_en && depth == B[DEPTHw-1 : 0] && !rd_en) begin
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if (wr_en && depth == B[DEPTHw-1 : 0] && !rd_en) begin
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$display(" %t: ERROR: Attempt to write to full FIFO: %m",$time);
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$display(" %t: ERROR: Attempt to write to full FIFO: %m",$time);
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$finish;
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$finish;
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end
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end
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if (rd_en && depth == {DEPTHw{1'b0}}) begin
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if (rd_en && depth == {DEPTHw{1'b0}}) begin
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