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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [input_ports.sv] - Diff between revs 54 and 56

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Rev 54	Rev 56
Line 26...	Line 26...
`** NoC router input Port. It consists of input buffer, control FIFO`	`** NoC router input Port. It consists of input buffer, control FIFO`
`** and request masking/generation control modules`	`** and request masking/generation control modules`
`**`	`**`
`**************************************************************/`	`**************************************************************/`

	`module input_ports #(`
	`parameter NOC_ID=0,`

`module input_ports`
`import pronoc_pkg::*;`
`#(`
`parameter P=5`	`parameter P=5`
`)(`	`)(`
`current_r_addr,`	`current_r_addr,`
`neighbors_r_addr,`	`neighbors_r_addr,`
`ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,`	`ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,`
Line 70...	Line 66...
`credit_init_val_out,`	`credit_init_val_out,`
`reset,`	`reset,`
`clk`	`clk`
`);`	`);`

	`NOC_CONF

`localparam`	`localparam`
`PV = V * P,`	`PV = V * P,`
`VV = V * V,`	`VV = V * V,`
`PVV = PV * V,`	`PVV = PV * V,`
Line 88...	Line 84...
`WPP = WP * P,`	`WPP = WP * P,`
`PVDSTPw= PV * DSTPw,`	`PVDSTPw= PV * DSTPw,`
`PRAw= P * RAw;`	`PRAw= P * RAw;`



`input reset,clk;`	`input reset,clk;`
`input [RAw-1 : 0] current_r_addr;`	`input [RAw-1 : 0] current_r_addr;`
`input [PRAw-1: 0] neighbors_r_addr;`	`input [PRAw-1: 0] neighbors_r_addr;`
`output [PV-1 : 0] ivc_num_getting_sw_grant;`	`output [PV-1 : 0] ivc_num_getting_sw_grant;`
`input [P-1 : 0] any_ivc_sw_request_granted_all;`	`input [P-1 : 0] any_ivc_sw_request_granted_all;`
Line 111...	Line 106...
`input [PV-1 : 0] sel;`	`input [PV-1 : 0] sel;`
`input [PPSw-1 : 0] port_pre_sel;`	`input [PPSw-1 : 0] port_pre_sel;`
`input [PV-1 : 0] swap_port_presel;`	`input [PV-1 : 0] swap_port_presel;`
`input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;`	`input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;`


`output [WP-1 : 0] iport_weight_all;`	`output [WP-1 : 0] iport_weight_all;`
`output [PV-1 : 0] vc_weight_is_consumed_all;`	`output [PV-1 : 0] vc_weight_is_consumed_all;`
`output [P-1 : 0] iport_weight_is_consumed_all;`	`output [P-1 : 0] iport_weight_is_consumed_all;`
`input [PP_1-1 : 0] granted_dest_port_all;`	`input [PP_1-1 : 0] granted_dest_port_all;`
`output [WPP-1 : 0] oports_weight_all;`	`output [WPP-1 : 0] oports_weight_all;`



`output ivc_info_t ivc_info [P-1 : 0][V-1 : 0];`	`output ivc_info_t ivc_info [P-1 : 0][V-1 : 0];`
`input vsa_ctrl_t vsa_ctrl_in [P-1: 0];`	`input vsa_ctrl_t vsa_ctrl_in [P-1: 0];`
`input ssa_ctrl_t ssa_ctrl_in [P-1: 0];`	`input ssa_ctrl_t ssa_ctrl_in [P-1: 0];`
`input smart_ctrl_t smart_ctrl_in [P-1 : 0];`	`input smart_ctrl_t smart_ctrl_in [P-1 : 0];`
`output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];`	`output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];`
Line 134...	Line 126...

`genvar i;`	`genvar i;`
`generate`	`generate`
`for(i=0;i`	`for(i=0;i`




`input_queue_per_port`	`input_queue_per_port`
`// iport_reg_base`	`// iport_reg_base`
`#(`	`#(`
	`.NOC_ID(NOC_ID),`
`.SW_LOC(i),`	`.SW_LOC(i),`
`.P(P)`	`.P(P)`
`)`	`) the_input_queue_per_port (`
`the_input_queue_per_port`
`(`
`.credit_out(credit_out_all [(i+1)V-1 : iV]),`	`.credit_out(credit_out_all [(i+1)V-1 : iV]),`
`.current_r_addr(current_r_addr),`	`.current_r_addr(current_r_addr),`
`.neighbors_r_addr(neighbors_r_addr),`	`.neighbors_r_addr(neighbors_r_addr),`
`.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant [(i+1)V-1 : iV]),// for non spec ivc_num_getting_first_sw_grant,`	`.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant [(i+1)V-1 : iV]),// for non spec ivc_num_getting_first_sw_grant,`
`.any_ivc_sw_request_granted(any_ivc_sw_request_granted_all [i]),`	`.any_ivc_sw_request_granted(any_ivc_sw_request_granted_all [i]),`
Line 178...	Line 166...
`.ivc_info(ivc_info[i]),`	`.ivc_info(ivc_info[i]),`
`.vsa_ctrl_in(vsa_ctrl_in [i]),`	`.vsa_ctrl_in(vsa_ctrl_in [i]),`
`.smart_ctrl_in(smart_ctrl_in [i]),`	`.smart_ctrl_in(smart_ctrl_in [i]),`
`.ssa_ctrl_in(ssa_ctrl_in [i]),`	`.ssa_ctrl_in(ssa_ctrl_in [i]),`
`.credit_init_val_out(credit_init_val_out[i])`	`.credit_init_val_out(credit_init_val_out[i])`

`);`	`);`

`end//for`	`end//for`
`endgenerate`	`endgenerate`

Line 193...	Line 180...

`input_queue_per_port`	`input_queue_per_port`

`**************************/`	`**************************/`

`module input_queue_per_port`	`module input_queue_per_port #(`
`import pronoc_pkg::*;`	`parameter NOC_ID=0,`
`#(`
`parameter P = 5, // router port num`	`parameter P = 5, // router port num`
`parameter SW_LOC = 0`	`parameter SW_LOC = 0`
`)(`	`)(`
`current_r_addr,`	`current_r_addr,`
`credit_out,`	`credit_out,`
Line 234...	Line 220...
`vsa_ctrl_in,`	`vsa_ctrl_in,`
`ssa_ctrl_in,`	`ssa_ctrl_in,`
`credit_init_val_out`	`credit_init_val_out`
`);`	`);`

	`NOC_CONF



`localparam`	`localparam`
`PORT_B = port_buffer_size(SW_LOC),`	`PORT_B = port_buffer_size(SW_LOC),`
`PORT_Bw= log2(PORT_B);`	`PORT_Bw= log2(PORT_B);`



`localparam`	`localparam`
`VV = V * V,`	`VV = V * V,`
`VDSTPw = V * DSTPw,`	`VDSTPw = V * DSTPw,`
`W = WEIGHTw,`	`W = WEIGHTw,`
`WP = W * P,`	`WP = W * P,`
Line 406...	Line 388...
`end`	`end`


`//extract header flit info`	`//extract header flit info`
`extract_header_flit_info #(`	`extract_header_flit_info #(`
	`.NOC_ID(NOC_ID),`
`.DATA_w(0)`	`.DATA_w(0)`
`)`	`) header_extractor (`
`header_extractor`
`(`
`.flit_in(flit_in),`	`.flit_in(flit_in),`
`.flit_in_wr(flit_in_wr),`	`.flit_in_wr(flit_in_wr),`
`.class_o(class_in),`	`.class_o(class_in),`
`.destport_o(destport_in),`	`.destport_o(destport_in),`
`.dest_e_addr_o(dest_e_addr_in),`	`.dest_e_addr_o(dest_e_addr_in),`
Line 436...	Line 417...
`/* verilator lint_on WIDTH */`	`/* verilator lint_on WIDTH */`



`mesh_tori_endp_addr_decode #(`	`mesh_tori_endp_addr_decode #(`
`.TOPOLOGY("MESH"),`	`.TOPOLOGY(TOPOLOGY),`
`.T1(T1),`	`.T1(T1),`
`.T2(T2),`	`.T2(T2),`
`.T3(T3),`	`.T3(T3),`
`.EAw(EAw)`	`.EAw(EAw)`
`)`	`)`
Line 717...	Line 698...
`//TODO remove multiple_dest[i] to see if it works?`	`//TODO remove multiple_dest[i] to see if it works?`

`assign clear_dspt_mulicast [i] = (reset_ivc[i] & multiple_dest[i]) ? dest_port_encoded[i] : {DSTPw{1'b0}};`	`assign clear_dspt_mulicast [i] = (reset_ivc[i] & multiple_dest[i]) ? dest_port_encoded[i] : {DSTPw{1'b0}};`

`// a fix priority arbiter.`	`// a fix priority arbiter.`
`multicast_dst_sel sel(`	`multicast_dst_sel #(`
	`.NOC_ID(NOC_ID)`
	`) sel_arb(`
`.destport_in(dest_port_multi[i]),`	`.destport_in(dest_port_multi[i]),`
`.destport_out(dest_port_encoded[i])`	`.destport_out(dest_port_encoded[i])`
`);`	`);`

`//check if we have multiple port to send a packet to`	`//check if we have multiple port to send a packet to`
Line 972...	Line 955...
`end`	`end`
`*/`	`*/`


`flit_buffer #(`	`flit_buffer #(`
	`.V(V),`
`.B(PORT_B), // buffer space :flit per VC`	`.B(PORT_B), // buffer space :flit per VC`
`.SSA_EN(SSA_EN)`	`.SSA_EN(SSA_EN),`
	`.Fw(Fw),`
	`.PCK_TYPE(PCK_TYPE),`
	`.CAST_TYPE(CAST_TYPE),`
	`.DEBUG_EN(DEBUG_EN)`
`)`	`)`
`the_flit_buffer`	`the_flit_buffer`
`(`	`(`

`.din(flit_in), // Data in`	`.din(flit_in), // Data in`
Line 997...	Line 985...

`end else begin :spec//not nonspec comb`	`end else begin :spec//not nonspec comb`


`flit_buffer #(`	`flit_buffer #(`
	`.V(V),`
`.B(PORT_B), // buffer space :flit per VC`	`.B(PORT_B), // buffer space :flit per VC`
`.SSA_EN(SSA_EN)`	`.SSA_EN(SSA_EN),`
	`.Fw(Fw),`
	`.PCK_TYPE(PCK_TYPE),`
	`.CAST_TYPE(CAST_TYPE),`
	`.DEBUG_EN(DEBUG_EN)`
`)`	`)`
`the_flit_buffer`	`the_flit_buffer`
`(`	`(`
`.din(flit_in), // Data in`	`.din(flit_in), // Data in`
`.vc_num_wr(vc_num_in),//write virtual channel`	`.vc_num_wr(vc_num_in),//write virtual channel`
Line 1025...	Line 1018...

`/* verilator lint_off WIDTH */`	`/* verilator lint_off WIDTH */`
`if(CAST_TYPE== "UNICAST") begin : unicast`	`if(CAST_TYPE== "UNICAST") begin : unicast`
`/* verilator lint_on WIDTH */`	`/* verilator lint_on WIDTH */`
`look_ahead_routing #(`	`look_ahead_routing #(`
	`.NOC_ID(NOC_ID),`
`.T1(T1),`	`.T1(T1),`
`.T2(T2),`	`.T2(T2),`
`.T3(T3),`	`.T3(T3),`
`.T4(T4),`	`.T4(T4),`
`.P(P),`	`.P(P),`
Line 1052...	Line 1046...
`.reset(reset),`	`.reset(reset),`
`.clk(clk)`	`.clk(clk)`
`);`	`);`
`end // unicast`	`end // unicast`



`endgenerate`	`endgenerate`



`header_flit_update_lk_route_ovc #(`	`header_flit_update_lk_route_ovc #(`
	`.NOC_ID(NOC_ID),`
`.P(P)`	`.P(P)`
`)`	`) the_flit_update (`
`the_flit_update`
`(`
`.flit_in (buffer_out),`	`.flit_in (buffer_out),`
`.flit_out (flit_out),`	`.flit_out (flit_out),`
`.vc_num_in(ivc_num_getting_sw_grant),`	`.vc_num_in(ivc_num_getting_sw_grant),`
`.lk_dest_all_in (lk_destination_encoded),`	`.lk_dest_all_in (lk_destination_encoded),`
`.assigned_ovc_num (assigned_ovc_num),`	`.assigned_ovc_num (assigned_ovc_num),`
Line 1076...	Line 1067...
`.reset (reset),`	`.reset (reset),`
`.clk (clk)`	`.clk (clk)`
`);`	`);`



`//synthesis translate_off`	`//synthesis translate_off`
`//synopsys translate_off`	`//synopsys translate_off`
`generate`	`generate`
`if(DEBUG_EN) begin :debg`	`if(DEBUG_EN) begin :debg`



`always @ (posedge clk) begin`	`always @ (posedge clk) begin`
`if((\|vsa_ctrl_in.ivc_num_getting_sw_grant) & (\|ssa_ctrl_in.ivc_num_getting_sw_grant))begin`	`if((\|vsa_ctrl_in.ivc_num_getting_sw_grant) & (\|ssa_ctrl_in.ivc_num_getting_sw_grant))begin`
`$display("%t: ERROR: VSA/SSA conflict: an input port cannot get both sva and ssa grant at the same time %m",$time);`	`$display("%t: ERROR: VSA/SSA conflict: an input port cannot get both sva and ssa grant at the same time %m",$time);`
`$finish;`	`$finish;`
`end`	`end`
Line 1157...	Line 1145...
`genvar j;`	`genvar j;`
`reg[V-1 :0] t1;`	`reg[V-1 :0] t1;`
`generate`	`generate`
`for (j=0;j`	`for (j=0;j`
`always @(posedge clk) begin`	`always @(posedge clk) begin`
`if(reset)begin`	if(`pronoc_reset)begin
`t1[j]<=1'b0;`	`t1[j]<=1'b0;`
`end else begin`	`end else begin`
`if(flit_in_wr >0 && vc_num_in[j] && t1[j]==0)begin`	`if(flit_in_wr >0 && vc_num_in[j] && t1[j]==0)begin`
`$display("%t : Parser:current_r=%h, class_in=%h, destport_in=%h, dest_e_addr_in=%h, src_e_addr_in=%h, vc_num_in=%h,hdr_flit_wr=%h, hdr_flg_in=%h,tail_flg_in=%h ",$time,current_r_addr, class_in, destport_in, dest_e_addr_in, src_e_addr_in, vc_num_in,hdr_flit_wr, hdr_flg_in,tail_flg_in);`	`$display("%t : Parser:current_r=%h, class_in=%h, destport_in=%h, dest_e_addr_in=%h, src_e_addr_in=%h, vc_num_in=%h,hdr_flit_wr=%h, hdr_flg_in=%h,tail_flg_in=%h ",$time,current_r_addr, class_in, destport_in, dest_e_addr_in, src_e_addr_in, vc_num_in,hdr_flit_wr, hdr_flg_in,tail_flg_in);`
`t1[j]<=1;`	`t1[j]<=1;`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [input_ports.sv] - Diff between revs 54 and 56