URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [iport_reg_base.sv] - Diff between revs 54 and 56

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Rev 54	Rev 56
Line 34...	Line 34...
`iport_reg_base`	`iport_reg_base`

`**************************/`	`**************************/`

`module iport_reg_base #(`	`module iport_reg_base #(`
	`parameter NOC_ID=0,`
`parameter PCK_TYPE = "MULTI_FLIT",`	`parameter PCK_TYPE = "MULTI_FLIT",`
`parameter V = 4, // vc_num_per_port`	`parameter V = 4, // vc_num_per_port`
`parameter P = 5, // router port num`	`parameter P = 5, // router port num`
`parameter B = 4, // buffer space :flit per VC`	`parameter B = 4, // buffer space :flit per VC`
`parameter T1= 8,`	`parameter T1= 8,`
Line 64...	Line 65...
`parameter SWA_ARBITER_TYPE ="RRA",// "RRA","WRRA"`	`parameter SWA_ARBITER_TYPE ="RRA",// "RRA","WRRA"`
`parameter WEIGHTw=4,`	`parameter WEIGHTw=4,`
`parameter WRRA_CONFIG_INDEX=0,`	`parameter WRRA_CONFIG_INDEX=0,`
`parameter PPSw=4,`	`parameter PPSw=4,`
`parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.`	`parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.`
`parameter BYTE_EN=0`	`parameter BYTE_EN=0,`
	`parameter CAST_TYPE= "UNICAST"`

`)(`	`)(`
`current_r_addr,`	`current_r_addr,`
`neighbors_r_addr,`	`neighbors_r_addr,`
`ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,`	`ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,`
Line 183...	Line 185...
`wire [ELw-1 : 0] endp_l_in;`	`wire [ELw-1 : 0] endp_l_in;`
`logic [WEIGHTw-1 : 0] iport_weight_next;`	`logic [WEIGHTw-1 : 0] iport_weight_next;`

`//extract header flit info`	`//extract header flit info`
`extract_header_flit_info #(`	`extract_header_flit_info #(`
	`.NOC_ID(NOC_ID),`
`.DATA_w(0)`	`.DATA_w(0)`
`)`	`) header_extractor (`
`header_extractor`
`(`
`.flit_in(flit_in),`	`.flit_in(flit_in),`
`.flit_in_wr(flit_in_wr),`	`.flit_in_wr(flit_in_wr),`
`.class_o(class_in),`	`.class_o(class_in),`
`.destport_o(destport_in),`	`.destport_o(destport_in),`
`.dest_e_addr_o(dest_e_addr_in),`	`.dest_e_addr_o(dest_e_addr_in),`
Line 203...	Line 204...
`.be_o( ),`	`.be_o( ),`
`.data_o( )`	`.data_o( )`
`);`	`);`




`// synopsys translate_off`	`// synopsys translate_off`
`// synthesis translate_off`	`// synthesis translate_off`
`ifdef MONITORE_PATH	`ifdef MONITORE_PATH

`genvar j;`	`genvar j;`
Line 545...	Line 544...
`/* verilator lint_off WIDTH */`	`/* verilator lint_off WIDTH */`
`if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec`	`if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec`
`/* verilator lint_on WIDTH */`	`/* verilator lint_on WIDTH */`

`flit_buffer #(`	`flit_buffer #(`
	`.V(V),`
`.B(B), // buffer space :flit per VC`	`.B(B), // buffer space :flit per VC`
`.SSA_EN(SSA_EN)`	`.SSA_EN(SSA_EN),`
	`.Fw(Fw),`
	`.PCK_TYPE(PCK_TYPE),`
	`.CAST_TYPE(CAST_TYPE),`
	`.DEBUG_EN(DEBUG_EN)`

`)`	`)`
`the_flit_buffer`	`the_flit_buffer`
`(`	`(`
`.din(flit_in), // Data in`	`.din(flit_in), // Data in`
`.vc_num_wr(vc_num_in),//write vertual chanel`	`.vc_num_wr(vc_num_in),//write vertual chanel`
Line 575...	Line 580...
`wire [VCw-1 : 0] class_all;`	`wire [VCw-1 : 0] class_all;`



`flit_buffer_reg_base #(`	`flit_buffer_reg_base #(`
`.PCK_TYPE(PCK_TYPE),`	`.NOC_ID(NOC_ID),`
`.V(V),`	`.V(V),`
`.B(B),`	`.B(B),`
	`.SSA_EN(SSA_EN),`
`.Fpay(Fpay),`	`.Fpay(Fpay),`
`.DEBUG_EN(DEBUG_EN),`	`.DEBUG_EN(DEBUG_EN),`
	`.DSTPw(DSTPw),`
`.DSTPw(DSTPw)`	`.PCK_TYPE(PCK_TYPE),`
	`.CAST_TYPE(CAST_TYPE)`
`)`	`)`
`nn`	`nn`
`(`	`(`
`.din(flit_in),`	`.din(flit_in),`
`.vc_num_wr(vc_num_in),`	`.vc_num_wr(vc_num_in),`
Line 629...	Line 635...

`end else begin :spec//not nonspec comb`	`end else begin :spec//not nonspec comb`


`flit_buffer #(`	`flit_buffer #(`
	`.V(V),`
`.B(B), // buffer space :flit per VC`	`.B(B), // buffer space :flit per VC`
`.SSA_EN(SSA_EN)`	`.SSA_EN(SSA_EN),`
	`.Fw(Fw),`
	`.PCK_TYPE(PCK_TYPE),`
	`.CAST_TYPE(CAST_TYPE),`
	`.DEBUG_EN(DEBUG_EN)`
`)`	`)`
`the_flit_buffer`	`the_flit_buffer`
`(`	`(`
`.din(flit_in), // Data in`	`.din(flit_in), // Data in`
`.vc_num_wr(vc_num_in),//write vertual chanel`	`.vc_num_wr(vc_num_in),//write vertual chanel`
Line 666...	Line 677...
`.DSTPw(DSTPw),`	`.DSTPw(DSTPw),`
`.SW_LOC(SW_LOC),`	`.SW_LOC(SW_LOC),`
`.TOPOLOGY(TOPOLOGY),`	`.TOPOLOGY(TOPOLOGY),`
`.ROUTE_NAME(ROUTE_NAME),`	`.ROUTE_NAME(ROUTE_NAME),`
`.ROUTE_TYPE(ROUTE_TYPE)`	`.ROUTE_TYPE(ROUTE_TYPE)`
`)`	`) lk_routing (`
`lk_routing`
`(`
`.current_r_addr(current_r_addr),`	`.current_r_addr(current_r_addr),`
`.neighbors_r_addr(neighbors_r_addr),`	`.neighbors_r_addr(neighbors_r_addr),`
`.dest_e_addr(dest_e_addr_in),`	`.dest_e_addr(dest_e_addr_in),`
`.src_e_addr(src_e_addr_in),`	`.src_e_addr(src_e_addr_in),`
`.destport_encoded(destport_in_encoded),`	`.destport_encoded(destport_in_encoded),`
Line 680...	Line 689...
`.reset(reset),`	`.reset(reset),`
`.clk(clk)`	`.clk(clk)`
`);`	`);`

`header_flit_update_lk_route_ovc #(`	`header_flit_update_lk_route_ovc #(`
`.V(V),`	`.NOC_ID(NOC_ID),`
`.P(P),`	`.P(P)`
	`) the_flit_update (`
`.TOPOLOGY(TOPOLOGY),`
`.EAw(EAw),`
`.DSTPw(DSTPw),`
`.SSA_EN(SSA_EN),`
`.ROUTE_TYPE(ROUTE_TYPE)`

`)`
`the_flit_update`
`(`
`.flit_in (buffer_out),`	`.flit_in (buffer_out),`
`.flit_out (flit_out),`	`.flit_out (flit_out),`
`.vc_num_in(ivc_num_getting_sw_grant),`	`.vc_num_in(ivc_num_getting_sw_grant),`
`.lk_dest_all_in (lk_destination_encoded),`	`.lk_dest_all_in (lk_destination_encoded),`
`.assigned_ovc_num (assigned_ovc_num),`	`.assigned_ovc_num (assigned_ovc_num),`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [iport_reg_base.sv] - Diff between revs 54 and 56