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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [noc_top.sv] - Diff between revs 54 and 56

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Rev 54 Rev 56
Line 25... Line 25...
**
**
**************************************************************/
**************************************************************/
 
 
 
 
 
 
module  noc_top
module  noc_top #(
        import pronoc_pkg::*;
        parameter NOC_ID=0
(
) (
        reset,
        reset,
        clk,
        clk,
        chan_in_all,
        chan_in_all,
        chan_out_all,
        chan_out_all,
        router_event
        router_event
);
);
 
 
 
        `NOC_CONF
 
 
        input   clk,reset;
        input   clk,reset;
        //Endpoints ports
        //Endpoints ports
        input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
        input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
        output  smartflit_chanel_t chan_out_all [NE-1 : 0];
        output  smartflit_chanel_t chan_out_all [NE-1 : 0];
Line 50... Line 51...
 
 
        generate
        generate
        /* verilator lint_off WIDTH */
        /* verilator lint_off WIDTH */
        if (TOPOLOGY ==    "MESH" || TOPOLOGY ==    "FMESH" || TOPOLOGY ==  "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : tori_noc
        if (TOPOLOGY ==    "MESH" || TOPOLOGY ==    "FMESH" || TOPOLOGY ==  "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : tori_noc
        /* verilator lint_on WIDTH */
        /* verilator lint_on WIDTH */
                mesh_torus_noc_top noc_top (
                mesh_torus_noc_top #(
 
                        .NOC_ID(NOC_ID)
 
                ) noc_top (
                        .reset         (reset        ),
                        .reset         (reset        ),
                        .clk           (clk          ),
                        .clk           (clk          ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_out_all  (chan_out_all ),
                        .chan_out_all  (chan_out_all ),
                        .router_event  (router_event )
                        .router_event  (router_event )
                );
                );
 
 
 
 
    end else if (TOPOLOGY == "FATTREE") begin : fat_
    end else if (TOPOLOGY == "FATTREE") begin : fat_
 
 
        fattree_noc_top noc_top (
        fattree_noc_top #(
 
                        .NOC_ID(NOC_ID)
 
                ) noc_top (
                        .reset         (reset        ),
                        .reset         (reset        ),
                        .clk           (clk          ),
                        .clk           (clk          ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_out_all  (chan_out_all ),
                        .chan_out_all  (chan_out_all ),
                        .router_event  (router_event )
                        .router_event  (router_event )
        );
        );
 
 
 
 
    end else if (TOPOLOGY == "TREE") begin : tree_
    end else if (TOPOLOGY == "TREE") begin : tree_
        tree_noc_top  noc_top (
        tree_noc_top  #(
 
                        .NOC_ID(NOC_ID)
 
                ) noc_top (
                .reset         (reset        ),
                .reset         (reset        ),
                .clk           (clk          ),
                .clk           (clk          ),
                .chan_in_all   (chan_in_all  ),
                .chan_in_all   (chan_in_all  ),
                .chan_out_all  (chan_out_all ),
                .chan_out_all  (chan_out_all ),
                .router_event  (router_event )
                .router_event  (router_event )
        );
        );
    end else if (TOPOLOGY == "STAR") begin : star_
    end else if (TOPOLOGY == "STAR") begin : star_
        star_noc_top  noc_top (
        star_noc_top  #(
 
                        .NOC_ID(NOC_ID)
 
                ) noc_top (
                        .reset         (reset        ),
                        .reset         (reset        ),
                        .clk           (clk          ),
                        .clk           (clk          ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_out_all  (chan_out_all ),
                        .chan_out_all  (chan_out_all ),
                        .router_event  (router_event )
                        .router_event  (router_event )
                );
                );
 
 
    end else begin :custom_
    end else begin :custom_
 
 
        custom_noc_top noc_top (
        custom_noc_top #(
 
                        .NOC_ID(NOC_ID)
 
                ) noc_top (
                        .reset         (reset        ),
                        .reset         (reset        ),
                        .clk           (clk          ),
                        .clk           (clk          ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_out_all  (chan_out_all ),
                        .chan_out_all  (chan_out_all ),
                        .router_event  (router_event )
                        .router_event  (router_event )
Line 111... Line 121...
/**********************************
/**********************************
The noc top module that can be called in Verilog module.
The noc top module that can be called in Verilog module.
 
 
***********************************/
***********************************/
 
 
module  noc_top_v
module  noc_top_v  #(
   import pronoc_pkg::*;
        parameter NOC_ID=0
   (
)(
    flit_out_all,
    flit_out_all,
    flit_out_wr_all,
    flit_out_wr_all,
    credit_in_all,
    credit_in_all,
    flit_in_all,
    flit_in_all,
    flit_in_wr_all,
    flit_in_wr_all,
    credit_out_all,
    credit_out_all,
    reset,
    reset,
    clk
    clk
 );
 );
 
 
 
        `NOC_CONF
 
 
        input   clk,reset;
        input   clk,reset;
        output [NEFw-1 : 0] flit_out_all;
        output [NEFw-1 : 0] flit_out_all;
    output [NE-1 : 0] flit_out_wr_all;
    output [NE-1 : 0] flit_out_wr_all;
    input  [NEV-1 : 0] credit_in_all;
    input  [NEV-1 : 0] credit_in_all;
Line 138... Line 149...
 
 
        //struct typed array ports which cannot be caled in verilog
        //struct typed array ports which cannot be caled in verilog
        smartflit_chanel_t chan_in_all  [NE-1 : 0];
        smartflit_chanel_t chan_in_all  [NE-1 : 0];
        smartflit_chanel_t chan_out_all [NE-1 : 0];
        smartflit_chanel_t chan_out_all [NE-1 : 0];
 
 
        noc_top the_top(
        noc_top  #(
 
                .NOC_ID(NOC_ID)
 
        ) the_top(
                .reset(reset),
                .reset(reset),
                .clk(clk),
                .clk(clk),
                .chan_in_all(chan_in_all),
                .chan_in_all(chan_in_all),
                .chan_out_all(chan_out_all),
                .chan_out_all(chan_out_all),
                .router_event  (  )
                .router_event  (  )
        );
        );
 
 
 
 
 
 
 
 
        genvar i;
        genvar i;
        generate
        generate
        for (i=0; i
        for (i=0; i
                assign chan_in_all[i].flit_chanel.flit    = flit_in_all [Fw*(i+1)-1 : Fw*i];
                assign chan_in_all[i].flit_chanel.flit    = flit_in_all [Fw*(i+1)-1 : Fw*i];
                assign chan_in_all[i].flit_chanel.credit  = credit_in_all [V*(i+1)-1 : V*i];
                assign chan_in_all[i].flit_chanel.credit  = credit_in_all [V*(i+1)-1 : V*i];

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