`include "pronoc_def.v"
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`include "pronoc_def.v"
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/****************************
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/****************************
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* This module can inject and eject packets from the NoC.
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* This module can inject and eject packets from the NoC.
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* It can be used in simulation for injecting real application traces to the NoC
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* It can be used in simulation for injecting real application traces to the NoC
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* *************************/
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* *************************/
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module packet_injector
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module packet_injector #(
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import pronoc_pkg::*;
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parameter NOC_ID=0
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(
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) (
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//general
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//general
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current_e_addr,
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current_e_addr,
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reset,
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reset,
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clk,
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clk,
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//noc port
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//noc port
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chan_in,
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chan_in,
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chan_out,
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chan_out,
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//control interafce
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//control interafce
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pck_injct_in,
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pck_injct_in,
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pck_injct_out
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pck_injct_out
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);
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);
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`NOC_CONF
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//general
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//general
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input reset,clk;
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input reset,clk;
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input [EAw-1 :0 ] current_e_addr;
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input [EAw-1 :0 ] current_e_addr;
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// the destination endpoint address
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// the destination endpoint address
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//NoC interface
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//NoC interface
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input smartflit_chanel_t chan_in;
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input smartflit_chanel_t chan_in;
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output smartflit_chanel_t chan_out;
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output smartflit_chanel_t chan_out;
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//control interafce
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//control interafce
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input pck_injct_t pck_injct_in;
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input pck_injct_t pck_injct_in;
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output pck_injct_t pck_injct_out;
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output pck_injct_t pck_injct_out;
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wire [RAw-1 :0 ] current_r_addr;
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wire [RAw-1 :0 ] current_r_addr;
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wire [DSTPw-1 : 0 ] destport;
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wire [DSTPw-1 : 0 ] destport;
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reg flit_wr;
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reg flit_wr;
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assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
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assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
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generate if(CAST_TYPE == "UNICAST") begin : uni
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generate if(CAST_TYPE == "UNICAST") begin : uni
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conventional_routing #(
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conventional_routing #(
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.NOC_ID(NOC_ID),
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.TOPOLOGY(TOPOLOGY),
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.TOPOLOGY(TOPOLOGY),
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.ROUTE_NAME(ROUTE_NAME),
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.ROUTE_NAME(ROUTE_NAME),
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.ROUTE_TYPE(ROUTE_TYPE),
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.ROUTE_TYPE(ROUTE_TYPE),
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.T1(T1),
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.T1(T1),
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.T2(T2),
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.T2(T2),
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.T3(T3),
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.T3(T3),
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.RAw(RAw),
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.RAw(RAw),
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.EAw(EAw),
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.EAw(EAw),
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.DSTPw(DSTPw),
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.DSTPw(DSTPw),
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.LOCATED_IN_NI(1)
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.LOCATED_IN_NI(1)
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)
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)
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routing_module
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routing_module
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(
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(
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.current_r_addr(current_r_addr),
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.current_r_addr(current_r_addr),
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.dest_e_addr(pck_injct_in.endp_addr),
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.dest_e_addr(pck_injct_in.endp_addr),
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.src_e_addr(current_e_addr),
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.src_e_addr(current_e_addr),
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.destport(destport)
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.destport(destport)
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);
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);
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end endgenerate
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end endgenerate
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localparam
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localparam
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HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
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HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
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HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
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HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
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HDR_DATA_w =
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HDR_DATA_w =
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(PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
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(PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
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(HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp;
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(HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp;
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wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
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wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
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wire [Fw-1 : 0] hdr_flit_out;
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wire [Fw-1 : 0] hdr_flit_out;
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header_flit_generator #(
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header_flit_generator #(
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.NOC_ID(NOC_ID),
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.DATA_w(HDR_DATA_w)
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.DATA_w(HDR_DATA_w)
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)
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) the_header_flit_generator (
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the_header_flit_generator
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(
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.flit_out (hdr_flit_out),
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.flit_out (hdr_flit_out),
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.vc_num_in (pck_injct_in.vc),
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.vc_num_in (pck_injct_in.vc),
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.class_in (pck_injct_in.class_num),
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.class_in (pck_injct_in.class_num),
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.dest_e_addr_in (pck_injct_in.endp_addr),
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.dest_e_addr_in (pck_injct_in.endp_addr),
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.src_e_addr_in (current_e_addr),
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.src_e_addr_in (current_e_addr),
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.weight_in (pck_injct_in.init_weight),
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.weight_in (pck_injct_in.init_weight),
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.destport_in (destport),
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.destport_in (destport),
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.data_in (hdr_data_in),
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.data_in (hdr_data_in),
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.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
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.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
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);
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);
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localparam
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localparam
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REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,
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REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,
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REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
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REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
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REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
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REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
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REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
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REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
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CNTw = log2(REMAIN_DAT_FLIT),
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CNTw = log2(REMAIN_DAT_FLIT),
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MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
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MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
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logic [PCK_SIZw-1 : 0] counter, counter_next;
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logic [PCK_SIZw-1 : 0] counter, counter_next;
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logic [CNTw-1 : 0] counter2,counter2_next;
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logic [CNTw-1 : 0] counter2,counter2_next;
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reg tail,head;
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reg tail,head;
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wire [Fpay -1 : 0] remain_dat [REMAIN_DAT_FLIT -1 : 0];
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wire [Fpay -1 : 0] remain_dat [REMAIN_DAT_FLIT -1 : 0];
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wire [Fpay-1 : 0] dataIn = remain_dat[counter2];
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wire [Fpay-1 : 0] dataIn = remain_dat[counter2];
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enum bit [2:0] {HEADER, BODY,TAIL} flit_type,flit_type_next;
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enum bit [2:0] {HEADER, BODY,TAIL} flit_type,flit_type_next;
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wire [V-1 : 0] wr_vc_send = (flit_wr)? pck_injct_in.vc : {V{1'b0}};
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wire [V-1 : 0] wr_vc_send = (flit_wr)? pck_injct_in.vc : {V{1'b0}};
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wire [V-1 : 0] vc_fifo_full;
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wire [V-1 : 0] vc_fifo_full;
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wire noc_ready;
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wire noc_ready;
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localparam
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localparam
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LAST_TMP =PCK_INJ_Dw - (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
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LAST_TMP =PCK_INJ_Dw - (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
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LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
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LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
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genvar i;
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genvar i;
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generate
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generate
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for(i=0; i
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for(i=0; i
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assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1 : (Fpay*i)+HDR_DATA_w];
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assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1 : (Fpay*i)+HDR_DATA_w];
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end
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end
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if(REMAIN_DAT_FLIT_F ) begin :flt
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if(REMAIN_DAT_FLIT_F ) begin :flt
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assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1 : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];
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assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1 : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];
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end
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end
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endgenerate
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endgenerate
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one_hot_mux #(
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one_hot_mux #(
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.IN_WIDTH (V ),
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.IN_WIDTH (V ),
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.SEL_WIDTH (V ),
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.SEL_WIDTH (V ),
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.OUT_WIDTH (1 )
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.OUT_WIDTH (1 )
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) one_hot_mux1 (
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) one_hot_mux1 (
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.mux_in (~ vc_fifo_full ),
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.mux_in (~ vc_fifo_full ),
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.mux_out (noc_ready ),
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.mux_out (noc_ready ),
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.sel (pck_injct_in.vc ));
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.sel (pck_injct_in.vc ));
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always @ (*) begin
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always @ (*) begin
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counter_next = counter;
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counter_next = counter;
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counter2_next =counter2;
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counter2_next =counter2;
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flit_type_next =flit_type;
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flit_type_next =flit_type;
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tail=1'b0;
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tail=1'b0;
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head=1'b0;
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head=1'b0;
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flit_wr=0;
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flit_wr=0;
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if(noc_ready)begin
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if(noc_ready)begin
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case(flit_type)
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case(flit_type)
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HEADER:begin
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HEADER:begin
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if(pck_injct_in.pck_wr)begin
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if(pck_injct_in.pck_wr)begin
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flit_wr=1;
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flit_wr=1;
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counter_next = pck_injct_in.size-1;
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counter_next = pck_injct_in.size-1;
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counter2_next=0;
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counter2_next=0;
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head=1'b1;
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head=1'b1;
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if(pck_injct_in.size == 1)begin
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if(pck_injct_in.size == 1)begin
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tail=1'b1;
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tail=1'b1;
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end else if (pck_injct_in.size == 2) begin
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end else if (pck_injct_in.size == 2) begin
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flit_type_next = TAIL;
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flit_type_next = TAIL;
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end else begin
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end else begin
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flit_type_next = BODY;
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flit_type_next = BODY;
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end
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end
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end
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end
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end
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end
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BODY: begin
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BODY: begin
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flit_wr=1;
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flit_wr=1;
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counter_next = counter -1'b1;
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counter_next = counter -1'b1;
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counter2_next =counter2 +1'b1;
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counter2_next =counter2 +1'b1;
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if(counter == 2) begin
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if(counter == 2) begin
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flit_type_next = TAIL;
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flit_type_next = TAIL;
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end
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end
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end
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end
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TAIL: begin
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TAIL: begin
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flit_type_next = HEADER;
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flit_type_next = HEADER;
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flit_wr=1;
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flit_wr=1;
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tail=1'b1;
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tail=1'b1;
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end
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end
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default: begin
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default: begin
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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logic [V-1 : 0] credit_o, credit_o_next;
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logic [V-1 : 0] credit_o, credit_o_next;
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//pronoc_register #(.W(3),.RESET_TO(HEADER) ) reg1 (.in(flit_type_next ), .out(flit_type), .reset(reset), .clk(clk));
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//pronoc_register #(.W(3),.RESET_TO(HEADER) ) reg1 (.in(flit_type_next ), .out(flit_type), .reset(reset), .clk(clk));
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pronoc_register #(.W(PCK_SIZw)) reg2 (.in(counter_next ), .out(counter), .reset(reset), .clk(clk));
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pronoc_register #(.W(PCK_SIZw)) reg2 (.in(counter_next ), .out(counter), .reset(reset), .clk(clk));
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pronoc_register #(.W(CNTw)) reg3 (.in(counter2_next ), .out(counter2), .reset(reset), .clk(clk));
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pronoc_register #(.W(CNTw)) reg3 (.in(counter2_next ), .out(counter2), .reset(reset), .clk(clk));
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pronoc_register #(.W(V)) reg4 (.in(credit_o_next ), .out(credit_o), .reset(reset), .clk(clk));
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pronoc_register #(.W(V)) reg4 (.in(credit_o_next ), .out(credit_o), .reset(reset), .clk(clk));
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always @ (*) begin
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always @ (*) begin
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credit_o_next = credit_o;
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credit_o_next = credit_o;
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if (chan_in.flit_chanel.flit_wr) credit_o_next = chan_in.flit_chanel.flit.vc;
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if (chan_in.flit_chanel.flit_wr) credit_o_next = chan_in.flit_chanel.flit.vc;
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else credit_o_next = {V{1'b0}};
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else credit_o_next = {V{1'b0}};
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end
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end
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always @(`pronoc_clk_reset_edge)begin
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always @(`pronoc_clk_reset_edge)begin
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if(`pronoc_reset) flit_type<=HEADER;
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if(`pronoc_reset) flit_type<=HEADER;
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else flit_type <= flit_type_next;
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else flit_type <= flit_type_next;
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end
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end
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injector_ovc_status #(
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injector_ovc_status #(
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.V(V),
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.V(V),
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.B(LB),
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.B(LB),
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.CRDTw(CRDTw)
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.CRDTw(CRDTw)
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)
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)
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the_ovc_status
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the_ovc_status
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(
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(
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.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
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.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
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.wr_in(wr_vc_send),
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.wr_in(wr_vc_send),
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.credit_in(chan_in.flit_chanel.credit),
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.credit_in(chan_in.flit_chanel.credit),
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.full_vc(vc_fifo_full),
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.full_vc(vc_fifo_full),
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.nearly_full_vc( ),
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.nearly_full_vc( ),
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.empty_vc( ),
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.empty_vc( ),
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.clk(clk),
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.clk(clk),
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.reset(reset)
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.reset(reset)
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);
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);
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wire [HDR_DATA_w-1 : 0] hdr_data_o;
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wire [HDR_DATA_w-1 : 0] hdr_data_o;
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hdr_flit_t hdr_flit_i;
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hdr_flit_t hdr_flit_i;
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header_flit_info
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header_flit_info #(
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#(
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.NOC_ID (NOC_ID),
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.DATA_w (HDR_DATA_w )
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.DATA_w (HDR_DATA_w )
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) extractor (
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) extractor (
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.flit(chan_in.flit_chanel.flit),
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.flit(chan_in.flit_chanel.flit),
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.hdr_flit(hdr_flit_i),
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.hdr_flit(hdr_flit_i),
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.data_o(hdr_data_o)
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.data_o(hdr_data_o)
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);
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);
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wire [PCK_INJ_Dw-1 : 0] pck_data_o [V-1 : 0];
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wire [PCK_INJ_Dw-1 : 0] pck_data_o [V-1 : 0];
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reg [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];
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reg [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];
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genvar k;
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genvar k;
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reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];
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reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];
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reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];
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reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];
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logic [15:0] h2t_counter [V-1 : 0];
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logic [15:0] h2t_counter [V-1 : 0];
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logic [15:0] h2t_counter_next [V-1 : 0];
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logic [15:0] h2t_counter_next [V-1 : 0];
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//synthesis translate_off
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//synthesis translate_off
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wire [NEw-1 : 0] current_id;
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wire [NEw-1 : 0] current_id;
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wire [NEw-1 : 0] sendor_id;
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wire [NEw-1 : 0] sendor_id;
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endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));
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endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));
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endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr[EAw-1 : 0]));
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endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr[EAw-1 : 0]));
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//synthesis translate_on
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//synthesis translate_on
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wire [NE-1 :0] dest_mcast_all_endp;
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wire [NE-1 :0] dest_mcast_all_endp;
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generate
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generate
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if(CAST_TYPE != "UNICAST") begin
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if(CAST_TYPE != "UNICAST") begin
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mcast_dest_list_decode decode (
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mcast_dest_list_decode #(
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.NOC_ID(NOC_ID)
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) decode (
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.dest_e_addr(hdr_flit_i.dest_e_addr),
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.dest_e_addr(hdr_flit_i.dest_e_addr),
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.dest_o(dest_mcast_all_endp),
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.dest_o(dest_mcast_all_endp),
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.row_has_any_dest(),
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.row_has_any_dest(),
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.is_unicast()
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.is_unicast()
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);
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);
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end
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end
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for(i=0; i
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for(i=0; i
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always@(*) begin
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always@(*) begin
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h2t_counter_next[i]=h2t_counter[i]+1'b1;
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h2t_counter_next[i]=h2t_counter[i]+1'b1;
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if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin
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if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin
|
h2t_counter_next[i]= 16'd0; // reset once header flit is received
|
h2t_counter_next[i]= 16'd0; // reset once header flit is received
|
end//hdr flit wr
|
end//hdr flit wr
|
end//always
|
end//always
|
|
|
|
|
|
|
|
|
always @ (`pronoc_clk_reset_edge )begin
|
always @ (`pronoc_clk_reset_edge )begin
|
if(`pronoc_reset) begin
|
if(`pronoc_reset) begin
|
rsv_counter[i]<= {PCK_SIZw{1'b0}};
|
rsv_counter[i]<= {PCK_SIZw{1'b0}};
|
h2t_counter[i]<= 16'd0;
|
h2t_counter[i]<= 16'd0;
|
sender_endp_addr_reg [i]<= {EAw{1'b0}};
|
sender_endp_addr_reg [i]<= {EAw{1'b0}};
|
end else begin
|
end else begin
|
h2t_counter[i]<=h2t_counter_next[i];
|
h2t_counter[i]<=h2t_counter_next[i];
|
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
|
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
|
if(chan_in.flit_chanel.flit.hdr_flag)begin
|
if(chan_in.flit_chanel.flit.hdr_flag)begin
|
rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
|
rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
|
sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;
|
sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;
|
//synthesis translate_off
|
//synthesis translate_off
|
if(CAST_TYPE == "UNICAST") begin
|
if(CAST_TYPE == "UNICAST") begin
|
if(hdr_flit_i.dest_e_addr[EAw-1:0] != current_e_addr) begin
|
if(hdr_flit_i.dest_e_addr[EAw-1:0] != current_e_addr) begin
|
$display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
|
$display("%t: ERROR: packet destination address %d does not match receiver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
|
$finish;
|
$finish;
|
end//if hdr_flit_i
|
end//if hdr_flit_i
|
end else begin
|
end else begin
|
if(dest_mcast_all_endp[current_id] !=1'b1 ) begin
|
if(dest_mcast_all_endp[current_id] !=1'b1 ) begin
|
$display("%t: ERROR: packet destination address %b does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr ,current_id );
|
$display("%t: ERROR: packet destination address %b does not match receiver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr ,current_id );
|
$finish;
|
$finish;
|
end
|
end
|
end//if hdr_flit_i
|
end//if hdr_flit_i
|
//synthesis translate_on
|
//synthesis translate_on
|
end //if hdr_flag
|
end //if hdr_flag
|
else rsv_counter[i]<= rsv_counter[i]+1'b1;
|
else rsv_counter[i]<= rsv_counter[i]+1'b1;
|
end//flit wr
|
end//flit wr
|
end//reset
|
end//reset
|
end//always
|
end//always
|
|
|
|
|
|
|
|
|
for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
|
for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
|
|
|
always @ (`pronoc_clk_reset_edge )begin
|
always @ (`pronoc_clk_reset_edge )begin
|
if(`pronoc_reset) begin
|
if(`pronoc_reset) begin
|
pck_data_o_gen [i][k] <= {Fpay{1'b0}};
|
pck_data_o_gen [i][k] <= {Fpay{1'b0}};
|
|
|
end else begin
|
end else begin
|
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
|
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
|
if (chan_in.flit_chanel.flit.hdr_flag )begin
|
if (chan_in.flit_chanel.flit.hdr_flag )begin
|
if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;
|
if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;
|
end
|
end
|
else begin
|
else begin
|
if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload[Fpay-1 : 0];
|
if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload[Fpay-1 : 0];
|
|
|
end // else
|
end // else
|
end //if
|
end //if
|
end //else
|
end //else
|
end// always
|
end// always
|
|
|
if (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];
|
if (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];
|
else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];
|
else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];
|
else assign pck_data_o [i][(k)*Fpay+HDR_DATA_w -1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];
|
else assign pck_data_o [i][(k)*Fpay+HDR_DATA_w -1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];
|
|
|
end //for k
|
end //for k
|
|
|
|
|
//synthesis translate_off
|
//synthesis translate_off
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin
|
if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin
|
$display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);
|
$display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);
|
$finish;
|
$finish;
|
end
|
end
|
|
|
end
|
end
|
//synthesis translate_on
|
//synthesis translate_on
|
|
|
|
|
|
|
|
|
end//for i
|
end//for i
|
endgenerate
|
endgenerate
|
|
|
wire [V-1 : 0] vc_reg;
|
wire [V-1 : 0] vc_reg;
|
wire tail_flag_reg, hdr_flag_reg;
|
wire tail_flag_reg, hdr_flag_reg;
|
|
|
|
|
pronoc_register #(.W(V)) register1 (.in(chan_in.flit_chanel.flit.vc), .reset (reset ), .clk (clk),.out(vc_reg));
|
pronoc_register #(.W(V)) register1 (.in(chan_in.flit_chanel.flit.vc), .reset (reset ), .clk (clk),.out(vc_reg));
|
pronoc_register #(.W(1)) register2 (.in(chan_in.flit_chanel.flit.hdr_flag), .reset (reset ), .clk (clk),.out(hdr_flag_reg));
|
pronoc_register #(.W(1)) register2 (.in(chan_in.flit_chanel.flit.hdr_flag), .reset (reset ), .clk (clk),.out(hdr_flag_reg));
|
pronoc_register #(.W(1)) register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset (reset ), .clk (clk),.out(tail_flag_reg));
|
pronoc_register #(.W(1)) register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset (reset ), .clk (clk),.out(tail_flag_reg));
|
|
|
wire [Vw-1 : 0] vc_bin;
|
wire [Vw-1 : 0] vc_bin;
|
|
|
one_hot_to_bin #(
|
one_hot_to_bin #(
|
.ONE_HOT_WIDTH (V),
|
.ONE_HOT_WIDTH (V),
|
.BIN_WIDTH (Vw )
|
.BIN_WIDTH (Vw )
|
) one_hot_to_bin (
|
) one_hot_to_bin (
|
.one_hot_code (vc_reg ),
|
.one_hot_code (vc_reg ),
|
.bin_code (vc_bin )
|
.bin_code (vc_bin )
|
);
|
);
|
|
|
|
|
assign pck_injct_out.data = pck_data_o[vc_bin];
|
assign pck_injct_out.data = pck_data_o[vc_bin];
|
assign pck_injct_out.size = rsv_counter[vc_bin];
|
assign pck_injct_out.size = rsv_counter[vc_bin];
|
assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];
|
assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];
|
assign pck_injct_out.ready = (flit_type == HEADER)? ~vc_fifo_full : {V{1'b0}};
|
assign pck_injct_out.ready = (flit_type == HEADER)? ~vc_fifo_full : {V{1'b0}};
|
assign pck_injct_out.endp_addr[EAw-1 : 0] = sender_endp_addr_reg[vc_bin];
|
assign pck_injct_out.endp_addr[EAw-1 : 0] = sender_endp_addr_reg[vc_bin];
|
assign pck_injct_out.vc = vc_reg;
|
assign pck_injct_out.vc = vc_reg;
|
assign pck_injct_out.pck_wr = tail_flag_reg;
|
assign pck_injct_out.pck_wr = tail_flag_reg;
|
|
|
assign chan_out.flit_chanel.flit.hdr_flag =head;
|
assign chan_out.flit_chanel.flit.hdr_flag =head;
|
assign chan_out.flit_chanel.flit.tail_flag=tail;
|
assign chan_out.flit_chanel.flit.tail_flag=tail;
|
assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
|
assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
|
assign chan_out.flit_chanel.flit_wr=flit_wr;
|
assign chan_out.flit_chanel.flit_wr=flit_wr;
|
|
|
generate
|
generate
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(PCK_TYPE == "SINGLE_FLIT" ) begin : single_f
|
if(PCK_TYPE == "SINGLE_FLIT" ) begin : single_f
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
assign chan_out.flit_chanel.flit.payload = hdr_flit_out[FPAYw-1 : 0];
|
assign chan_out.flit_chanel.flit.payload = hdr_flit_out[FPAYw-1 : 0];
|
end else begin
|
end else begin
|
assign chan_out.flit_chanel.flit.payload = (flit_type== HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;
|
assign chan_out.flit_chanel.flit.payload = (flit_type== HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
|
assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
|
assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
|
assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
|
assign chan_out.flit_chanel.credit= credit_o;
|
assign chan_out.flit_chanel.credit= credit_o;
|
assign chan_out.ctrl_chanel.credit_init_val= LB;
|
assign chan_out.ctrl_chanel.credit_init_val= LB;
|
assign chan_out.ctrl_chanel.credit_release_en={V{1'b0}};
|
assign chan_out.ctrl_chanel.credit_release_en={V{1'b0}};
|
assign chan_out.ctrl_chanel.endp_port =1'b1;
|
assign chan_out.ctrl_chanel.endp_port =1'b1;
|
|
|
|
|
|
|
distance_gen #(
|
distance_gen #(
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.EAw(EAw),
|
.EAw(EAw),
|
.DISTw(DISTw)
|
.DISTw(DISTw)
|
)
|
)
|
the_distance_gen
|
the_distance_gen
|
(
|
(
|
.src_e_addr(sender_endp_addr_reg[vc_bin]),
|
.src_e_addr(sender_endp_addr_reg[vc_bin]),
|
.dest_e_addr(current_e_addr),
|
.dest_e_addr(current_e_addr),
|
.distance(pck_injct_out.distance)
|
.distance(pck_injct_out.distance)
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
//synthesis translate_off
|
//synthesis translate_off
|
//`define MONITOR_RSV_DAT
|
//`define MONITOR_RSV_DAT
|
|
|
|
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin
|
if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin
|
$display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);
|
$display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);
|
$finish;
|
$finish;
|
end
|
end
|
if(pck_injct_in.pck_wr && (pck_injct_in.size
|
if(pck_injct_in.pck_wr && (pck_injct_in.size
|
$display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );
|
$display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );
|
$finish;
|
$finish;
|
end
|
end
|
|
|
`ifdef MONITOR_RSV_DAT
|
`ifdef MONITOR_RSV_DAT
|
|
|
|
|
if(pck_injct_in.pck_wr) begin
|
if(pck_injct_in.pck_wr) begin
|
$display ("pck_inj(%d) send a packet: size=%d, data=%h, v=%h",current_id,
|
$display ("pck_inj(%d) send a packet: size=%d, data=%h, v=%h",current_id,
|
pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);
|
pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);
|
end
|
end
|
|
|
if(pck_injct_out.pck_wr) begin
|
if(pck_injct_out.pck_wr) begin
|
$display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,
|
$display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,
|
sendor_id,pck_injct_out.size,pck_injct_out.data);
|
sendor_id,pck_injct_out.size,pck_injct_out.data);
|
end
|
end
|
|
|
|
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
|
|
//synthesis translate_on
|
//synthesis translate_on
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
/******************
|
/******************
|
* ovc_status
|
* ovc_status
|
*******************/
|
*******************/
|
|
|
module injector_ovc_status #(
|
module injector_ovc_status #(
|
parameter V = 4,
|
parameter V = 4,
|
parameter B = 16,
|
parameter B = 16,
|
parameter CRDTw =4
|
parameter CRDTw =4
|
)
|
)
|
(
|
(
|
|
|
input [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,
|
input [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,
|
input [V-1 :0] wr_in,
|
input [V-1 :0] wr_in,
|
input [V-1 :0] credit_in,
|
input [V-1 :0] credit_in,
|
output [V-1 :0] full_vc,
|
output [V-1 :0] full_vc,
|
output [V-1 :0] nearly_full_vc,
|
output [V-1 :0] nearly_full_vc,
|
output [V-1 :0] empty_vc,
|
output [V-1 :0] empty_vc,
|
input clk,
|
input clk,
|
input reset
|
input reset
|
);
|
);
|
|
|
|
|
function integer log2;
|
function integer log2;
|
input integer number; begin
|
input integer number; begin
|
log2=(number <=1) ? 1: 0;
|
log2=(number <=1) ? 1: 0;
|
while(2**log2
|
while(2**log2
|
log2=log2+1;
|
log2=log2+1;
|
end
|
end
|
end
|
end
|
endfunction // log2
|
endfunction // log2
|
|
|
|
|
localparam DEPTH_WIDTH = log2(B+1);
|
localparam DEPTH_WIDTH = log2(B+1);
|
|
|
|
|
reg [DEPTH_WIDTH-1 : 0] credit [V-1 : 0];
|
reg [DEPTH_WIDTH-1 : 0] credit [V-1 : 0];
|
wire [V-1 : 0] cand_vc_next;
|
wire [V-1 : 0] cand_vc_next;
|
|
|
|
|
genvar i;
|
genvar i;
|
generate
|
generate
|
for(i=0;i
|
for(i=0;i
|
always @ (`pronoc_clk_reset_edge )begin
|
always @ (`pronoc_clk_reset_edge )begin
|
if(`pronoc_reset) begin
|
if(`pronoc_reset) begin
|
credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
|
credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
|
end else begin
|
end else begin
|
if( wr_in[i] && ~credit_in[i]) credit[i] <= credit[i]-1'b1;
|
if( wr_in[i] && ~credit_in[i]) credit[i] <= credit[i]-1'b1;
|
if( ~wr_in[i] && credit_in[i]) credit[i] <= credit[i]+1'b1;
|
if( ~wr_in[i] && credit_in[i]) credit[i] <= credit[i]+1'b1;
|
end //reset
|
end //reset
|
end//always
|
end//always
|
|
|
assign full_vc[i] = (credit[i] == {DEPTH_WIDTH{1'b0}});
|
assign full_vc[i] = (credit[i] == {DEPTH_WIDTH{1'b0}});
|
assign nearly_full_vc[i]= (credit[i] == 1) | full_vc[i];
|
assign nearly_full_vc[i]= (credit[i] == 1) | full_vc[i];
|
assign empty_vc[i] = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
|
assign empty_vc[i] = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
|
end//for
|
end//for
|
endgenerate
|
endgenerate
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
/**************************************
|
/**************************************
|
*
|
*
|
*
|
*
|
* ***********************************/
|
* ***********************************/
|
|
|
|
|
|
|
module packet_injector_verilator
|
module packet_injector_verilator #(
|
import pronoc_pkg::*;
|
parameter NOC_ID=0
|
(
|
) (
|
//general
|
//general
|
current_e_addr,
|
current_e_addr,
|
reset,
|
reset,
|
clk,
|
clk,
|
//noc port
|
//noc port
|
chan_in,
|
chan_in,
|
chan_out,
|
chan_out,
|
//control interafce
|
//control interafce
|
pck_injct_in_data,
|
pck_injct_in_data,
|
pck_injct_in_size,
|
pck_injct_in_size,
|
pck_injct_in_endp_addr,
|
pck_injct_in_endp_addr,
|
pck_injct_in_class_num,
|
pck_injct_in_class_num,
|
pck_injct_in_init_weight,
|
pck_injct_in_init_weight,
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pck_injct_in_vc,
|
pck_injct_in_vc,
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pck_injct_in_pck_wr,
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pck_injct_in_pck_wr,
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pck_injct_in_ready,
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pck_injct_in_ready,
|
|
|
pck_injct_out_data,
|
pck_injct_out_data,
|
pck_injct_out_size,
|
pck_injct_out_size,
|
pck_injct_out_endp_addr,
|
pck_injct_out_endp_addr,
|
pck_injct_out_class_num,
|
pck_injct_out_class_num,
|
pck_injct_out_init_weight,
|
pck_injct_out_init_weight,
|
pck_injct_out_vc,
|
pck_injct_out_vc,
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pck_injct_out_pck_wr,
|
pck_injct_out_pck_wr,
|
pck_injct_out_ready,
|
pck_injct_out_ready,
|
pck_injct_out_distance,
|
pck_injct_out_distance,
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pck_injct_out_h2t_delay,
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pck_injct_out_h2t_delay,
|
min_pck_size
|
min_pck_size
|
|
|
|
|
);
|
);
|
|
|
|
`NOC_CONF
|
|
|
//general
|
//general
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input reset,clk;
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input reset,clk;
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input [EAw-1 :0 ] current_e_addr;
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input [EAw-1 :0 ] current_e_addr;
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|
|
// the destination endpoint address
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// the destination endpoint address
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//NoC interface
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//NoC interface
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input smartflit_chanel_t chan_in;
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input smartflit_chanel_t chan_in;
|
output smartflit_chanel_t chan_out;
|
output smartflit_chanel_t chan_out;
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//control interafce
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//control interafce
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|
|
|
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input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;
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input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;
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input [PCK_SIZw-1 : 0] pck_injct_in_size;
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input [PCK_SIZw-1 : 0] pck_injct_in_size;
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input [DAw-1 : 0] pck_injct_in_endp_addr;
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input [DAw-1 : 0] pck_injct_in_endp_addr;
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input [Cw-1 : 0] pck_injct_in_class_num;
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input [Cw-1 : 0] pck_injct_in_class_num;
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input [WEIGHTw-1 : 0] pck_injct_in_init_weight;
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input [WEIGHTw-1 : 0] pck_injct_in_init_weight;
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input [V-1 : 0] pck_injct_in_vc;
|
input [V-1 : 0] pck_injct_in_vc;
|
input pck_injct_in_pck_wr;
|
input pck_injct_in_pck_wr;
|
input [V-1 : 0] pck_injct_in_ready;
|
input [V-1 : 0] pck_injct_in_ready;
|
|
|
output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;
|
output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;
|
output [PCK_SIZw-1 : 0] pck_injct_out_size;
|
output [PCK_SIZw-1 : 0] pck_injct_out_size;
|
output [DAw-1 : 0] pck_injct_out_endp_addr;
|
output [DAw-1 : 0] pck_injct_out_endp_addr;
|
output [Cw-1 : 0] pck_injct_out_class_num;
|
output [Cw-1 : 0] pck_injct_out_class_num;
|
output [WEIGHTw-1 : 0] pck_injct_out_init_weight;
|
output [WEIGHTw-1 : 0] pck_injct_out_init_weight;
|
output [V-1 : 0] pck_injct_out_vc;
|
output [V-1 : 0] pck_injct_out_vc;
|
output pck_injct_out_pck_wr;
|
output pck_injct_out_pck_wr;
|
output [V-1 : 0] pck_injct_out_ready;
|
output [V-1 : 0] pck_injct_out_ready;
|
output [DISTw-1 : 0] pck_injct_out_distance;
|
output [DISTw-1 : 0] pck_injct_out_distance;
|
output [15 : 0] pck_injct_out_h2t_delay;
|
output [15 : 0] pck_injct_out_h2t_delay;
|
output [4 : 0] min_pck_size;
|
output [4 : 0] min_pck_size;
|
|
|
pck_injct_t pck_injct_in;
|
pck_injct_t pck_injct_in;
|
pck_injct_t pck_injct_out;
|
pck_injct_t pck_injct_out;
|
|
|
assign pck_injct_in.data = pck_injct_in_data;
|
assign pck_injct_in.data = pck_injct_in_data;
|
assign pck_injct_in.size = pck_injct_in_size;
|
assign pck_injct_in.size = pck_injct_in_size;
|
assign pck_injct_in.endp_addr = pck_injct_in_endp_addr;
|
assign pck_injct_in.endp_addr = pck_injct_in_endp_addr;
|
assign pck_injct_in.class_num = pck_injct_in_class_num;
|
assign pck_injct_in.class_num = pck_injct_in_class_num;
|
assign pck_injct_in.init_weight = pck_injct_in_init_weight;
|
assign pck_injct_in.init_weight = pck_injct_in_init_weight;
|
assign pck_injct_in.vc = pck_injct_in_vc;
|
assign pck_injct_in.vc = pck_injct_in_vc;
|
assign pck_injct_in.pck_wr = pck_injct_in_pck_wr;
|
assign pck_injct_in.pck_wr = pck_injct_in_pck_wr;
|
assign pck_injct_in.ready = pck_injct_in_ready;
|
assign pck_injct_in.ready = pck_injct_in_ready;
|
|
|
assign pck_injct_out_data = pck_injct_out.data;
|
assign pck_injct_out_data = pck_injct_out.data;
|
assign pck_injct_out_size = pck_injct_out.size;
|
assign pck_injct_out_size = pck_injct_out.size;
|
assign pck_injct_out_endp_addr = pck_injct_out.endp_addr;
|
assign pck_injct_out_endp_addr = pck_injct_out.endp_addr;
|
assign pck_injct_out_class_num = pck_injct_out.class_num;
|
assign pck_injct_out_class_num = pck_injct_out.class_num;
|
assign pck_injct_out_init_weight = pck_injct_out.init_weight;
|
assign pck_injct_out_init_weight = pck_injct_out.init_weight;
|
assign pck_injct_out_vc = pck_injct_out.vc;
|
assign pck_injct_out_vc = pck_injct_out.vc;
|
assign pck_injct_out_pck_wr = pck_injct_out.pck_wr;
|
assign pck_injct_out_pck_wr = pck_injct_out.pck_wr;
|
assign pck_injct_out_ready = pck_injct_out.ready;
|
assign pck_injct_out_ready = pck_injct_out.ready;
|
assign pck_injct_out_distance = pck_injct_out.distance;
|
assign pck_injct_out_distance = pck_injct_out.distance;
|
assign pck_injct_out_h2t_delay = pck_injct_out.h2t_delay;
|
assign pck_injct_out_h2t_delay = pck_injct_out.h2t_delay;
|
|
|
packet_injector injector (
|
packet_injector #(
|
|
.NOC_ID(NOC_ID)
|
|
) injector (
|
.current_e_addr (current_e_addr ),
|
.current_e_addr (current_e_addr ),
|
.reset (reset ),
|
.reset (reset ),
|
.clk (clk ),
|
.clk (clk ),
|
.chan_in (chan_in ),
|
.chan_in (chan_in ),
|
.chan_out (chan_out ),
|
.chan_out (chan_out ),
|
.pck_injct_in (pck_injct_in ),
|
.pck_injct_in (pck_injct_in ),
|
.pck_injct_out (pck_injct_out ));
|
.pck_injct_out (pck_injct_out )
|
|
);
|
|
|
|
|
localparam
|
localparam
|
HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
|
HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
|
HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
|
HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
|
HDR_DATA_w =
|
HDR_DATA_w =
|
(PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
|
(PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
|
(HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp,
|
(HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp,
|
REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,
|
REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,
|
REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
|
REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
|
REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
|
REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
|
REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
|
REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
|
CNTw = log2(REMAIN_DAT_FLIT),
|
CNTw = log2(REMAIN_DAT_FLIT),
|
MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
|
MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
|
|
|
assign min_pck_size = MIN_PCK_SIZ[4:0];
|
assign min_pck_size = MIN_PCK_SIZ[4:0];
|
|
|
|
|
// `ifdef VERILATOR
|
// `ifdef VERILATOR
|
// logic endp_is_active /*verilator public_flat_rd*/ ;
|
// logic endp_is_active /*verilator public_flat_rd*/ ;
|
//
|
//
|
// always @ (*) begin
|
// always @ (*) begin
|
// endp_is_active = 1'b0;
|
// endp_is_active = 1'b0;
|
// if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
|
// if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
|
// if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
|
// if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
|
// if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
|
// if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
|
// end
|
// end
|
// `endif
|
// `endif
|
|
|
|
|
endmodule
|
endmodule
|
|
|
