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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [traffic_gen_top.sv] - Diff between revs 55 and 56

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Rev 55	Rev 56
Line 1...	Line 1...
`include "pronoc_def.v"	`include "pronoc_def.v"

`module traffic_gen_top`	`module traffic_gen_top #(`
`import pronoc_pkg::*;`	`parameter NOC_ID=0,`
`#(`
`parameter MAX_RATIO = 1000,`	`parameter MAX_RATIO = 1000,`
`parameter ENDP_ID = 100000`	`parameter ENDP_ID = 100000`
`)`	`)`
`(`	`(`

Line 44...	Line 43...
`reset,`	`reset,`
`clk`	`clk`

`);`	`);`


	`NOC_CONF



`localparam`	`localparam`
`RATIOw= $clog2(MAX_RATIO);`	`RATIOw= $clog2(MAX_RATIO);`

`// Vw = $clog2(V);`	`// Vw = $clog2(V);`

Line 58...	Line 62...


`localparam`	`localparam`
`PCK_CNTw = log2(MAX_PCK_NUM+1),`	`PCK_CNTw = log2(MAX_PCK_NUM+1),`
`CLK_CNTw = log2(MAX_SIM_CLKs+1),`	`CLK_CNTw = log2(MAX_SIM_CLKs+1),`
`PCK_SIZw = log2(MAX_PCK_SIZ+1),`
`AVG_PCK_SIZw = log2(10*MAX_PCK_SIZ+1),`	`AVG_PCK_SIZw = log2(10*MAX_PCK_SIZ+1),`
`/* verilator lint_off WIDTH */`	`/* verilator lint_off WIDTH */`
`DISTw = (TOPOLOGY=="FATTREE" \|\| TOPOLOGY=="TREE" ) ? log2(2*L+1): log2(NR+1),`
`W=WEIGHTw,`	`W=WEIGHTw,`
`PORT_B = (TOPOLOGY!="FMESH")? LB :`	`PORT_B = (TOPOLOGY!="FMESH")? LB :`
`(ENDP_ID < NE_MESH_TORI)? LB :B; // in FMESH, the buffer size of endpoints connected to edge routers non-local ports are B not LB`	`(ENDP_ID < NE_MESH_TORI)? LB :B; // in FMESH, the buffer size of endpoints connected to edge routers non-local ports are B not LB`
`/* verilator lint_on WIDTH */`	`/* verilator lint_on WIDTH */`
`input reset, clk;`	`input reset, clk;`
Line 141...	Line 143...

`reg inject_en,cand_wr_vc_en,pck_rd;`	`reg inject_en,cand_wr_vc_en,pck_rd;`
`reg [PCK_SIZw-1 :0] pck_size;`	`reg [PCK_SIZw-1 :0] pck_size;`
`logic [DAw-1 :0] dest_e_addr_reg,dest_e_addr_o;`	`logic [DAw-1 :0] dest_e_addr_reg,dest_e_addr_o;`





`// synopsys translate_off`	`// synopsys translate_off`
`// synthesis translate_off`	`// synthesis translate_off`

`ifdef MONITORE_PATH	`ifdef MONITORE_PATH


`reg tt;`	`reg tt;`
`always @(posedge clk) begin`	`always @(posedge clk) begin`
`if(reset)begin`	if(`pronoc_reset)begin
`tt<=1'b0;`	`tt<=1'b0;`
`end else begin`	`end else begin`
`if(flit_out_wr && tt==1'b0 )begin`	`if(flit_out_wr && tt==1'b0 )begin`
`$display( "%t: Injector: current_r_addr=%x,current_e_addr=%x,dest_e_addr=%x\n",$time, current_r_addr, current_e_addr, dest_e_addr);`	`$display( "%t: Injector: current_r_addr=%x,current_e_addr=%x,dest_e_addr=%x\n",$time, current_r_addr, current_e_addr, dest_e_addr);`
`tt<=1'b1;`	`tt<=1'b1;`
Line 164...	Line 170...

`// synthesis translate_on`	`// synthesis translate_on`
`// synopsys translate_on`	`// synopsys translate_on`






`localparam`	`localparam`
`HDR_DATA_w = (MIN_PCK_SIZE==1)? CLK_CNTw : 0,`	`HDR_DATA_w = (MIN_PCK_SIZE==1)? CLK_CNTw : 0,`
`HDR_Dw = (MIN_PCK_SIZE==1)? CLK_CNTw : 1;`	`HDR_Dw = (MIN_PCK_SIZE==1)? CLK_CNTw : 1;`

`wire [HDR_Dw-1 : 0] hdr_data_in,rd_hdr_data_out;`	`wire [HDR_Dw-1 : 0] hdr_data_in,rd_hdr_data_out;`
Line 211...	Line 213...
`wire [CLK_CNTw-1 : 0] hdr_flit_timestamp;`	`wire [CLK_CNTw-1 : 0] hdr_flit_timestamp;`
`wire pck_wr,buffer_full,pck_ready,valid_dst;`	`wire pck_wr,buffer_full,pck_ready,valid_dst;`
`wire [CLK_CNTw-1 : 0] rd_timestamp;`	`wire [CLK_CNTw-1 : 0] rd_timestamp;`



`logic [DELAYw-1 : 0] start_delay_counter,start_delay_counter_next;`	`logic [DELAYw-1 : 0] start_delay_counter,start_delay_counter_next;`
`logic start_en_next , start_en;`	`logic start_en_next , start_en;`

`pronoc_register #(.W(1)) streg1 (.reset(reset),.clk(clk), .in(start_en_next), .out(start_en) );`	`pronoc_register #(.W(1)) streg1 (.reset(reset),.clk(clk), .in(start_en_next), .out(start_en) );`
`pronoc_register #(.W(DELAYw)) streg2 (.reset(reset),.clk(clk), .in(start_delay_counter_next), .out(start_delay_counter) );`	`pronoc_register #(.W(DELAYw)) streg2 (.reset(reset),.clk(clk), .in(start_delay_counter_next), .out(start_delay_counter) );`



`always @(*) begin`	`always @(*) begin`
`start_en_next =start_en;`	`start_en_next =start_en;`
`start_delay_counter_next= start_delay_counter;`	`start_delay_counter_next= start_delay_counter;`
`if(start) begin`	`if(start) begin`
`start_en_next=1'b1;`	`start_en_next=1'b1;`
Line 236...	Line 235...
`end`	`end`
`end//always`	`end//always`

`wire start_injection = (start_delay_counter == start_delay);`	`wire start_injection = (start_delay_counter == start_delay);`




`check_destination_addr #(`	`check_destination_addr #(`
	`.NOC_ID(NOC_ID),`
`.TOPOLOGY(TOPOLOGY),`	`.TOPOLOGY(TOPOLOGY),`
`.T1(T1),`	`.T1(T1),`
`.T2(T2),`	`.T2(T2),`
`.T3(T3),`	`.T3(T3),`
`.EAw(EAw),`	`.EAw(EAw),`
`.SELF_LOOP_EN(SELF_LOOP_EN),`	`.SELF_LOOP_EN(SELF_LOOP_EN),`
`.DAw(DAw),`	`.DAw(DAw),`
`.CAST_TYPE(CAST_TYPE),`	`.CAST_TYPE(CAST_TYPE),`
`.NE(NE)`	`.NE(NE)`
`)`	`) check_destination_addr (`
`check_destination_addr(`
`.dest_e_addr(dest_e_addr),`	`.dest_e_addr(dest_e_addr),`
`.current_e_addr(current_e_addr),`	`.current_e_addr(current_e_addr),`
`.dest_is_valid(valid_dst)`	`.dest_is_valid(valid_dst)`
`);`	`);`


`//assign hdr_flit_sent=pck_rd;`	`//assign hdr_flit_sent=pck_rd;`

	`injection_ratio_ctrl # (`
`injection_ratio_ctrl #`
`(`
`.MAX_PCK_SIZ(MAX_PCK_SIZ),`	`.MAX_PCK_SIZ(MAX_PCK_SIZ),`
`.MAX_RATIO(MAX_RATIO)`	`.MAX_RATIO(MAX_RATIO)`
`)`	`) pck_inject_ratio_ctrl (`
`pck_inject_ratio_ctrl`
`(`
`.en(inject_en),`	`.en(inject_en),`
`.pck_size_in(pck_size_tmp),`	`.pck_size_in(pck_size_tmp),`
`.clk(clk),`	`.clk(clk),`
`.reset(reset),`	`.reset(reset),`
`.freez(buffer_full),`	`.freez(buffer_full),`
`.inject(pck_wr),`	`.inject(pck_wr),`
`.ratio(ratio)`	`.ratio(ratio)`
`);`	`);`



`output_vc_status #(`	`output_vc_status #(`
`.CRDTw(CRDTw),`	`.CRDTw(CRDTw),`
`.V (V),`	`.V (V),`
`.B (PORT_B)`	`.B (PORT_B)`
`)`	`) nic_ovc_status (`
`nic_ovc_status`
`(`
`.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),`	`.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),`
`.wr_in (ovc_wr_in),`	`.wr_in (ovc_wr_in),`
`.credit_in (credit_in),`	`.credit_in (credit_in),`
`.nearly_full_vc (nearly_full_vc),`	`.nearly_full_vc (nearly_full_vc),`
`.full_vc (full_vc),`	`.full_vc (full_vc),`
Line 298...	Line 286...
`.clk (clk),`	`.clk (clk),`
`.reset (reset)`	`.reset (reset)`
`);`	`);`




`packet_gen #(`	`packet_gen #(`
`.P(MAX_P),`	`.NOC_ID(NOC_ID),`
`.PCK_TYPE(PCK_TYPE),`	`.P(MAX_P)`
`.ROUTE_TYPE(ROUTE_TYPE),`	`) packet_buffer (`
`.MAX_PCK_NUM(MAX_PCK_NUM),`
`.MAX_SIM_CLKs(MAX_SIM_CLKs),`
`.TIMSTMP_FIFO_NUM(TIMSTMP_FIFO_NUM),`
`.MIN_PCK_SIZE(MIN_PCK_SIZE),`
`.MAX_PCK_SIZ(MAX_PCK_SIZ)`
`)`
`packet_buffer`
`(`
`.reset(reset),`	`.reset(reset),`
`.clk(clk),`	`.clk(clk),`
`.pck_wr(pck_wr),`	`.pck_wr(pck_wr),`
`.pck_rd(pck_rd),`	`.pck_rd(pck_rd),`
`.current_r_addr(current_r_addr),`	`.current_r_addr(current_r_addr),`
Line 331...	Line 309...
`.destport(destport),`	`.destport(destport),`
`.pck_size_in(pck_size_tmp),`	`.pck_size_in(pck_size_tmp),`
`.pck_size_o(pck_size)`	`.pck_size_o(pck_size)`
`);`	`);`





`assign wr_timestamp =pck_timestamp;`	`assign wr_timestamp =pck_timestamp;`

`assign update = flit_in_wr & flit_in[Fw-2];`	`assign update = flit_in_wr & flit_in[Fw-2];`
`assign hdr_flit = (flit_counter == 0);`	`assign hdr_flit = (flit_counter == 0);`
`assign tail_flit = (flit_counter == pck_size-1'b1);`	`assign tail_flit = (flit_counter == pck_size-1'b1);`



`assign time_stamp_h2h = hdr_flit_timestamp - rd_timestamp;`	`assign time_stamp_h2h = hdr_flit_timestamp - rd_timestamp;`
`assign time_stamp_h2t = clk_counter - rd_timestamp;`	`assign time_stamp_h2t = clk_counter - rd_timestamp;`

`wire [FPAYw-1 : 0] flit_out_pyload;`	`wire [FPAYw-1 : 0] flit_out_pyload;`
`wire [1 : 0] flit_out_hdr;`	`wire [1 : 0] flit_out_hdr;`


`wire [FPAYw-1 : 0] flit_out_header_pyload;`	`wire [FPAYw-1 : 0] flit_out_header_pyload;`
`wire [Fw-1 : 0] hdr_flit_out;`	`wire [Fw-1 : 0] hdr_flit_out;`





`assign hdr_data_in = (MIN_PCK_SIZE==1)? wr_timestamp[HDR_Dw-1 : 0] : {HDR_Dw{1'b0}};`	`assign hdr_data_in = (MIN_PCK_SIZE==1)? wr_timestamp[HDR_Dw-1 : 0] : {HDR_Dw{1'b0}};`

`header_flit_generator #(`	`header_flit_generator #(`
	`.NOC_ID(NOC_ID),`
`.DATA_w(HDR_DATA_w)`	`.DATA_w(HDR_DATA_w)`
`)`	`) the_header_flit_generator (`
`the_header_flit_generator`
`(`
`.flit_out(hdr_flit_out),`	`.flit_out(hdr_flit_out),`
`.vc_num_in(wr_vc),`	`.vc_num_in(wr_vc),`
`.class_in(pck_class_in),`	`.class_in(pck_class_in),`
`.dest_e_addr_in(dest_e_addr_o),`	`.dest_e_addr_in(dest_e_addr_o),`
`.src_e_addr_in(current_e_addr),`	`.src_e_addr_in(current_e_addr),`
Line 376...	Line 340...
`.data_in(hdr_data_in),`	`.data_in(hdr_data_in),`
`.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data`	`.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data`
`);`	`);`

`assign flit_out_class = pck_class_in;`	`assign flit_out_class = pck_class_in;`

`assign flit_out_hdr = {hdr_flit,tail_flit};`	`assign flit_out_hdr = {hdr_flit,tail_flit};`

`assign flit_out_header_pyload = hdr_flit_out[FPAYw-1 : 0];`	`assign flit_out_header_pyload = hdr_flit_out[FPAYw-1 : 0];`


`/* verilator lint_off WIDTH */`	`/* verilator lint_off WIDTH */`
`assign flit_out_pyload = (hdr_flit) ? flit_out_header_pyload :`	`assign flit_out_pyload = (hdr_flit) ? flit_out_header_pyload :`

`(tail_flit) ? wr_timestamp:`	`(tail_flit) ? wr_timestamp:`
`{pck_number,flit_counter};`	`{pck_number,flit_counter};`
`/* verilator lint_on WIDTH */`	`/* verilator lint_on WIDTH */`



`assign flit_out = {flit_out_hdr, wr_vc, flit_out_pyload };`	`assign flit_out = {flit_out_hdr, wr_vc, flit_out_pyload };`


`//extract header flit info`	`//extract header flit info`



`extract_header_flit_info #(`	`extract_header_flit_info #(`
	`.NOC_ID(NOC_ID),`
`.DATA_w(HDR_DATA_w)`	`.DATA_w(HDR_DATA_w)`
`)`	`) header_extractor (`
`header_extractor`
`(`
`.flit_in(flit_in),`	`.flit_in(flit_in),`
`.flit_in_wr(flit_in_wr),`	`.flit_in_wr(flit_in_wr),`
`.class_o(rd_class_hdr),`	`.class_o(rd_class_hdr),`
`.destport_o(),`	`.destport_o(),`
`.dest_e_addr_o(rd_des_e_addr),`	`.dest_e_addr_o(rd_des_e_addr),`
Line 426...	Line 381...
`.T1(T1),`	`.T1(T1),`
`.T2(T2),`	`.T2(T2),`
`.T3(T3),`	`.T3(T3),`
`.EAw(EAw),`	`.EAw(EAw),`
`.DISTw(DISTw)`	`.DISTw(DISTw)`
`)`	`) the_distance_gen (`
`the_distance_gen`
`(`
`.src_e_addr(src_e_addr),`	`.src_e_addr(src_e_addr),`
`.dest_e_addr(current_e_addr),`	`.dest_e_addr(current_e_addr),`
`.distance(distance)`	`.distance(distance)`
`);`	`);`

Line 475...	Line 428...


`assign ovc_wr_in = (flit_out_wr ) ? wr_vc : {V{1'b0}};`	`assign ovc_wr_in = (flit_out_wr ) ? wr_vc : {V{1'b0}};`

`/* verilator lint_off WIDTH */`	`/* verilator lint_off WIDTH */`
`assign wr_vc_is_full = (SSA_EN=="NO")? \| ( full_vc & wr_vc) : \| (nearly_full_vc & wr_vc);`	`//assign wr_vc_is_full = (SSA_EN=="NO")? \| ( full_vc & wr_vc) : \| (nearly_full_vc & wr_vc);`
	`assign wr_vc_is_full = \| ( full_vc & wr_vc);`
`/* verilator lint_on WIDTH */`	`/* verilator lint_on WIDTH */`


`generate`	`generate`
`/* verilator lint_off WIDTH */`	`/* verilator lint_off WIDTH */`
Line 646...	Line 600...
`/* verilator lint_on WIDTH */`	`/* verilator lint_on WIDTH */`

`wire [NEw-1 : 0] sum_temp;`	`wire [NEw-1 : 0] sum_temp;`
`wire is_unicast;`	`wire is_unicast;`

`mcast_dest_list_decode decode1 (`	`mcast_dest_list_decode #(`
	`.NOC_ID(NOC_ID)`
	`) decode1 (`
`.dest_e_addr(dest_e_addr_o),`	`.dest_e_addr(dest_e_addr_o),`
`.dest_o(dest_mcast_all_endp1),`	`.dest_o(dest_mcast_all_endp1),`
`.row_has_any_dest(),`	`.row_has_any_dest(),`
`.is_unicast(is_unicast)`	`.is_unicast(is_unicast)`
`);`	`);`
Line 710...	Line 666...


`wire [NE-1 :0] dest_mcast_all_endp2;`	`wire [NE-1 :0] dest_mcast_all_endp2;`
`generate`	`generate`
`if(CAST_TYPE != "UNICAST") begin :no_unicast`	`if(CAST_TYPE != "UNICAST") begin :no_unicast`
`mcast_dest_list_decode decode2 (`	`mcast_dest_list_decode #(`
	`.NOC_ID(NOC_ID)`
	`) decode2 (`
`.dest_e_addr(rd_des_e_addr),`	`.dest_e_addr(rd_des_e_addr),`
`.dest_o(dest_mcast_all_endp2),`	`.dest_o(dest_mcast_all_endp2),`
`.row_has_any_dest(),`	`.row_has_any_dest(),`
`.is_unicast()`	`.is_unicast()`
`);`	`);`
`end endgenerate`	`end`
	`endgenerate`



`always @(posedge clk) begin`	`always @(posedge clk) begin`
`/* verilator lint_off WIDTH */`	`/* verilator lint_off WIDTH */`
Line 845...	Line 804...
`// if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;`	`// if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;`
`// if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;`	`// if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;`
`// end`	`// end`
// `endif	// `endif


`endmodule`	`endmodule`





`/*****************************`	`/*****************************`
`injection_ratio_ctrl`	`injection_ratio_ctrl`

`*****************************/`	`*****************************/`
`module injection_ratio_ctrl #`	`module injection_ratio_ctrl #`
Line 982...	Line 937...
`packet_buffer`	`packet_buffer`
`**************************************/`	`**************************************/`


`module packet_gen`	`module packet_gen`
`import pronoc_pkg::*;`
`#(`	`#(`
`parameter P = 5,`	`parameter NOC_ID=0,`
`parameter PCK_TYPE = "SINGLE_FLIT",`	`parameter P = 5`
`parameter ROUTE_TYPE = "DETERMINISTIC",`
`parameter MAX_PCK_NUM = 10000,`
`parameter MAX_SIM_CLKs = 100000,`
`parameter TIMSTMP_FIFO_NUM=16,`
`parameter MIN_PCK_SIZE=2,`
`parameter MAX_PCK_SIZ=100`
`)(`	`)(`
`clk_counter,`	`clk_counter,`
`pck_wr,`	`pck_wr,`
`pck_rd,`	`pck_rd,`
`current_r_addr,`	`current_r_addr,`
Line 1013...	Line 961...
`clk,`	`clk,`
`reset`	`reset`
`);`	`);`


`function integer log2;`	`NOC_CONF
`input integer number; begin`
`log2=(number <=1) ? 1: 0;`
`while(2**log2`
`log2=log2+1;`
`end`
`end`
`endfunction // log2`

`localparam`	`localparam`
`PCK_CNTw = log2(MAX_PCK_NUM+1),`	`PCK_CNTw = log2(MAX_PCK_NUM+1),`
`CLK_CNTw = log2(MAX_SIM_CLKs+1),`	`CLK_CNTw = log2(MAX_SIM_CLKs+1);`
`PCK_SIZw = log2(MAX_PCK_SIZ);`

`input reset,clk, pck_wr, pck_rd;`	`input reset,clk, pck_wr, pck_rd;`
`input [RAw-1 :0] current_r_addr;`	`input [RAw-1 :0] current_r_addr;`
`input [EAw-1 : 0] current_e_addr;`	`input [EAw-1 : 0] current_e_addr;`
`input [CLK_CNTw-1 :0] clk_counter;`	`input [CLK_CNTw-1 :0] clk_counter;`
Line 1049...	Line 990...

`assign pck_ready = ~buffer_empty & valid_dst;`	`assign pck_ready = ~buffer_empty & valid_dst;`

`generate if(CAST_TYPE == "UNICAST") begin : uni`	`generate if(CAST_TYPE == "UNICAST") begin : uni`
`conventional_routing #(`	`conventional_routing #(`
	`.NOC_ID(NOC_ID),`
`.TOPOLOGY(TOPOLOGY),`	`.TOPOLOGY(TOPOLOGY),`
`.ROUTE_NAME(ROUTE_NAME),`	`.ROUTE_NAME(ROUTE_NAME),`
`.ROUTE_TYPE(ROUTE_TYPE),`	`.ROUTE_TYPE(ROUTE_TYPE),`
`.T1(T1),`	`.T1(T1),`
`.T2(T2),`	`.T2(T2),`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [traffic_gen_top.sv] - Diff between revs 55 and 56