`include "pronoc_def.v"
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`include "pronoc_def.v"
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module traffic_gen_top
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module traffic_gen_top #(
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import pronoc_pkg::*;
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parameter NOC_ID=0,
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#(
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parameter MAX_RATIO = 1000,
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parameter MAX_RATIO = 1000,
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parameter ENDP_ID = 100000
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parameter ENDP_ID = 100000
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)
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)
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(
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(
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//noc port
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//noc port
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chan_in,
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chan_in,
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chan_out,
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chan_out,
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//input
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//input
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ratio,// real injection ratio = (MAX_RATIO/100)*ratio
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ratio,// real injection ratio = (MAX_RATIO/100)*ratio
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pck_size_in,
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pck_size_in,
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current_e_addr,
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current_e_addr,
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dest_e_addr,
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dest_e_addr,
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pck_class_in,
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pck_class_in,
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start,
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start,
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stop,
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stop,
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report,
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report,
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init_weight,
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init_weight,
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start_delay,
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start_delay,
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//output
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//output
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pck_number,
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pck_number,
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sent_done, // tail flit has been sent
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sent_done, // tail flit has been sent
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hdr_flit_sent,
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hdr_flit_sent,
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update, // update the noc_analayzer
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update, // update the noc_analayzer
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src_e_addr,
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src_e_addr,
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flit_out_class,
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flit_out_class,
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flit_out_wr,
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flit_out_wr,
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flit_in_wr,
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flit_in_wr,
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distance,
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distance,
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pck_class_out,
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pck_class_out,
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time_stamp_h2h,
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time_stamp_h2h,
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time_stamp_h2t,
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time_stamp_h2t,
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pck_size_o,
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pck_size_o,
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mcast_dst_num_o,
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mcast_dst_num_o,
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reset,
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reset,
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clk
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clk
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);
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);
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`NOC_CONF
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localparam
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localparam
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RATIOw= $clog2(MAX_RATIO);
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RATIOw= $clog2(MAX_RATIO);
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// Vw = $clog2(V);
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// Vw = $clog2(V);
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input smartflit_chanel_t chan_in;
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input smartflit_chanel_t chan_in;
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output smartflit_chanel_t chan_out;
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output smartflit_chanel_t chan_out;
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localparam
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localparam
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PCK_CNTw = log2(MAX_PCK_NUM+1),
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PCK_CNTw = log2(MAX_PCK_NUM+1),
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CLK_CNTw = log2(MAX_SIM_CLKs+1),
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CLK_CNTw = log2(MAX_SIM_CLKs+1),
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PCK_SIZw = log2(MAX_PCK_SIZ+1),
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AVG_PCK_SIZw = log2(10*MAX_PCK_SIZ+1),
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AVG_PCK_SIZw = log2(10*MAX_PCK_SIZ+1),
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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DISTw = (TOPOLOGY=="FATTREE" || TOPOLOGY=="TREE" ) ? log2(2*L+1): log2(NR+1),
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W=WEIGHTw,
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W=WEIGHTw,
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PORT_B = (TOPOLOGY!="FMESH")? LB :
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PORT_B = (TOPOLOGY!="FMESH")? LB :
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(ENDP_ID < NE_MESH_TORI)? LB :B; // in FMESH, the buffer size of endpoints connected to edge routers non-local ports are B not LB
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(ENDP_ID < NE_MESH_TORI)? LB :B; // in FMESH, the buffer size of endpoints connected to edge routers non-local ports are B not LB
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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input reset, clk;
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input reset, clk;
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input [RATIOw-1 :0] ratio;
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input [RATIOw-1 :0] ratio;
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input start,stop;
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input start,stop;
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output update;
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output update;
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output [CLK_CNTw-1 :0] time_stamp_h2h,time_stamp_h2t;
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output [CLK_CNTw-1 :0] time_stamp_h2h,time_stamp_h2t;
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output [DISTw-1 :0] distance;
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output [DISTw-1 :0] distance;
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output [Cw-1 :0] pck_class_out;
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output [Cw-1 :0] pck_class_out;
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// the current endpoint address
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// the current endpoint address
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input [EAw-1 :0] current_e_addr;
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input [EAw-1 :0] current_e_addr;
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// the destination endpoint address
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// the destination endpoint address
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input [DAw-1 :0] dest_e_addr;
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input [DAw-1 :0] dest_e_addr;
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output [PCK_CNTw-1 :0] pck_number;
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output [PCK_CNTw-1 :0] pck_number;
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input [PCK_SIZw-1 :0] pck_size_in;
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input [PCK_SIZw-1 :0] pck_size_in;
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output reg sent_done;
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output reg sent_done;
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output reg hdr_flit_sent;
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output reg hdr_flit_sent;
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input [Cw-1 :0] pck_class_in;
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input [Cw-1 :0] pck_class_in;
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input [W-1 :0] init_weight;
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input [W-1 :0] init_weight;
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input report;
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input report;
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input [DELAYw-1 :0] start_delay;
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input [DELAYw-1 :0] start_delay;
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// the received packet source endpoint address
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// the received packet source endpoint address
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output [EAw-1 : 0] src_e_addr;
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output [EAw-1 : 0] src_e_addr;
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output [PCK_SIZw-1 : 0] pck_size_o;
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output [PCK_SIZw-1 : 0] pck_size_o;
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output [NEw-1 : 0] mcast_dst_num_o;
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output [NEw-1 : 0] mcast_dst_num_o;
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logic [Fw-1 :0] flit_out;
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logic [Fw-1 :0] flit_out;
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output logic flit_out_wr;
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output logic flit_out_wr;
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output [Cw-1 : 0] flit_out_class;
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output [Cw-1 : 0] flit_out_class;
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logic [V-1 :0] credit_in;
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logic [V-1 :0] credit_in;
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logic [Fw-1 :0] flit_in;
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logic [Fw-1 :0] flit_in;
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output logic flit_in_wr;
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output logic flit_in_wr;
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logic [V-1 :0] credit_out;
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logic [V-1 :0] credit_out;
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// the connected router address
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// the connected router address
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wire [RAw-1 :0] current_r_addr;
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wire [RAw-1 :0] current_r_addr;
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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wire [PCK_SIZw-1 : 0] pck_size_tmp= (PCK_TYPE == "SINGLE_FLIT" )? 1 : pck_size_in;
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wire [PCK_SIZw-1 : 0] pck_size_tmp= (PCK_TYPE == "SINGLE_FLIT" )? 1 : pck_size_in;
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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assign chan_out.flit_chanel.flit = flit_out;
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assign chan_out.flit_chanel.flit = flit_out;
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assign chan_out.flit_chanel.flit_wr = flit_out_wr;
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assign chan_out.flit_chanel.flit_wr = flit_out_wr;
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assign chan_out.flit_chanel.credit = credit_out;
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assign chan_out.flit_chanel.credit = credit_out;
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assign chan_out.smart_chanel = {SMART_CHANEL_w {1'b0}};
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assign chan_out.smart_chanel = {SMART_CHANEL_w {1'b0}};
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assign flit_in = chan_in.flit_chanel.flit;
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assign flit_in = chan_in.flit_chanel.flit;
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assign flit_in_wr= chan_in.flit_chanel.flit_wr;
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assign flit_in_wr= chan_in.flit_chanel.flit_wr;
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assign credit_in = chan_in.flit_chanel.credit;
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assign credit_in = chan_in.flit_chanel.credit;
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assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
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assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
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genvar i;
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genvar i;
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generate
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generate
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for (i=0; i
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for (i=0; i
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assign chan_out.ctrl_chanel.credit_init_val[i]= PORT_B;
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assign chan_out.ctrl_chanel.credit_init_val[i]= PORT_B;
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end
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end
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endgenerate
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endgenerate
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assign chan_out.ctrl_chanel.endp_port =1'b1;
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assign chan_out.ctrl_chanel.endp_port =1'b1;
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assign chan_out.ctrl_chanel.credit_release_en={V{1'b0}};
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assign chan_out.ctrl_chanel.credit_release_en={V{1'b0}};
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//old traffic.v file
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//old traffic.v file
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reg [2:0] ps,ns;
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reg [2:0] ps,ns;
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localparam IDEAL =3'b001, SENT =3'b010, WAIT=3'b100;
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localparam IDEAL =3'b001, SENT =3'b010, WAIT=3'b100;
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reg inject_en,cand_wr_vc_en,pck_rd;
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reg inject_en,cand_wr_vc_en,pck_rd;
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reg [PCK_SIZw-1 :0] pck_size;
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reg [PCK_SIZw-1 :0] pck_size;
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logic [DAw-1 :0] dest_e_addr_reg,dest_e_addr_o;
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logic [DAw-1 :0] dest_e_addr_reg,dest_e_addr_o;
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// synopsys translate_off
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// synopsys translate_off
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// synthesis translate_off
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// synthesis translate_off
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`ifdef MONITORE_PATH
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`ifdef MONITORE_PATH
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reg tt;
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reg tt;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if(reset)begin
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if(`pronoc_reset)begin
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tt<=1'b0;
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tt<=1'b0;
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end else begin
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end else begin
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if(flit_out_wr && tt==1'b0 )begin
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if(flit_out_wr && tt==1'b0 )begin
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$display( "%t: Injector: current_r_addr=%x,current_e_addr=%x,dest_e_addr=%x\n",$time, current_r_addr, current_e_addr, dest_e_addr);
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$display( "%t: Injector: current_r_addr=%x,current_e_addr=%x,dest_e_addr=%x\n",$time, current_r_addr, current_e_addr, dest_e_addr);
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tt<=1'b1;
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tt<=1'b1;
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end
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end
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end
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end
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end
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end
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`endif
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`endif
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// synthesis translate_on
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// synthesis translate_on
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// synopsys translate_on
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// synopsys translate_on
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localparam
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localparam
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HDR_DATA_w = (MIN_PCK_SIZE==1)? CLK_CNTw : 0,
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HDR_DATA_w = (MIN_PCK_SIZE==1)? CLK_CNTw : 0,
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HDR_Dw = (MIN_PCK_SIZE==1)? CLK_CNTw : 1;
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HDR_Dw = (MIN_PCK_SIZE==1)? CLK_CNTw : 1;
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wire [HDR_Dw-1 : 0] hdr_data_in,rd_hdr_data_out;
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wire [HDR_Dw-1 : 0] hdr_data_in,rd_hdr_data_out;
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pronoc_register #(.W(DAw)) reg2 (.in(dest_e_addr ), .out(dest_e_addr_reg), .reset(reset), .clk(clk));
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pronoc_register #(.W(DAw)) reg2 (.in(dest_e_addr ), .out(dest_e_addr_reg), .reset(reset), .clk(clk));
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wire [DSTPw-1 : 0] destport;
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wire [DSTPw-1 : 0] destport;
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wire [V-1 : 0] ovc_wr_in;
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wire [V-1 : 0] ovc_wr_in;
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wire [V-1 : 0] full_vc,empty_vc,nearly_full_vc;
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wire [V-1 : 0] full_vc,empty_vc,nearly_full_vc;
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reg [V-1 : 0] wr_vc,wr_vc_next;
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reg [V-1 : 0] wr_vc,wr_vc_next;
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wire [V-1 : 0] cand_vc;
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wire [V-1 : 0] cand_vc;
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wire [CLK_CNTw-1 : 0] wr_timestamp,pck_timestamp;
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wire [CLK_CNTw-1 : 0] wr_timestamp,pck_timestamp;
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wire hdr_flit,tail_flit;
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wire hdr_flit,tail_flit;
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reg [PCK_SIZw-1 : 0] flit_counter;
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reg [PCK_SIZw-1 : 0] flit_counter;
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reg flit_cnt_rst,flit_cnt_inc;
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reg flit_cnt_rst,flit_cnt_inc;
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wire rd_hdr_flg,rd_tail_flg;
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wire rd_hdr_flg,rd_tail_flg;
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wire [Cw-1 : 0] rd_class_hdr;
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wire [Cw-1 : 0] rd_class_hdr;
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// wire [P_1-1 : 0] rd_destport_hdr;
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// wire [P_1-1 : 0] rd_destport_hdr;
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wire [DAw-1 : 0] rd_des_e_addr;
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wire [DAw-1 : 0] rd_des_e_addr;
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wire [EAw-1 : 0] rd_src_e_addr;
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wire [EAw-1 : 0] rd_src_e_addr;
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reg [CLK_CNTw-1 : 0] rsv_counter;
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reg [CLK_CNTw-1 : 0] rsv_counter;
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reg [CLK_CNTw-1 : 0] clk_counter;
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reg [CLK_CNTw-1 : 0] clk_counter;
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wire [Vw-1 : 0] rd_vc_bin;//,wr_vc_bin;
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wire [Vw-1 : 0] rd_vc_bin;//,wr_vc_bin;
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reg [CLK_CNTw-1 : 0] rsv_time_stamp[V-1:0];
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reg [CLK_CNTw-1 : 0] rsv_time_stamp[V-1:0];
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reg [PCK_SIZw-1 : 0] rsv_pck_size [V-1:0];
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reg [PCK_SIZw-1 : 0] rsv_pck_size [V-1:0];
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wire [V-1 : 0] rd_vc;
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wire [V-1 : 0] rd_vc;
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wire wr_vc_is_full,wr_vc_avb,wr_vc_is_empty;
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wire wr_vc_is_full,wr_vc_avb,wr_vc_is_empty;
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reg [V-1 : 0] credit_out_next;
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reg [V-1 : 0] credit_out_next;
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reg [EAw-1 : 0] rsv_pck_src_e_addr [V-1:0];
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reg [EAw-1 : 0] rsv_pck_src_e_addr [V-1:0];
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reg [Cw-1 : 0] rsv_pck_class_in [V-1:0];
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reg [Cw-1 : 0] rsv_pck_class_in [V-1:0];
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wire [CLK_CNTw-1 : 0] hdr_flit_timestamp;
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wire [CLK_CNTw-1 : 0] hdr_flit_timestamp;
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wire pck_wr,buffer_full,pck_ready,valid_dst;
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wire pck_wr,buffer_full,pck_ready,valid_dst;
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wire [CLK_CNTw-1 : 0] rd_timestamp;
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wire [CLK_CNTw-1 : 0] rd_timestamp;
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logic [DELAYw-1 : 0] start_delay_counter,start_delay_counter_next;
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logic [DELAYw-1 : 0] start_delay_counter,start_delay_counter_next;
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logic start_en_next , start_en;
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logic start_en_next , start_en;
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pronoc_register #(.W(1)) streg1 (.reset(reset),.clk(clk), .in(start_en_next), .out(start_en) );
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pronoc_register #(.W(1)) streg1 (.reset(reset),.clk(clk), .in(start_en_next), .out(start_en) );
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pronoc_register #(.W(DELAYw)) streg2 (.reset(reset),.clk(clk), .in(start_delay_counter_next), .out(start_delay_counter) );
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pronoc_register #(.W(DELAYw)) streg2 (.reset(reset),.clk(clk), .in(start_delay_counter_next), .out(start_delay_counter) );
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always @(*) begin
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always @(*) begin
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start_en_next =start_en;
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start_en_next =start_en;
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start_delay_counter_next= start_delay_counter;
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start_delay_counter_next= start_delay_counter;
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if(start) begin
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if(start) begin
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start_en_next=1'b1;
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start_en_next=1'b1;
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start_delay_counter_next={DELAYw{1'b0}};
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start_delay_counter_next={DELAYw{1'b0}};
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end else if(start_en && ~inject_en) begin
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end else if(start_en && ~inject_en) begin
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start_delay_counter_next= start_delay_counter + 1'b1;
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start_delay_counter_next= start_delay_counter + 1'b1;
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end
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end
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if(stop) begin
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if(stop) begin
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start_en_next=1'b0;
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start_en_next=1'b0;
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end
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end
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end//always
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end//always
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wire start_injection = (start_delay_counter == start_delay);
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wire start_injection = (start_delay_counter == start_delay);
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check_destination_addr #(
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check_destination_addr #(
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.NOC_ID(NOC_ID),
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.TOPOLOGY(TOPOLOGY),
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.TOPOLOGY(TOPOLOGY),
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.T1(T1),
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.T1(T1),
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.T2(T2),
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.T2(T2),
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.T3(T3),
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.T3(T3),
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.EAw(EAw),
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.EAw(EAw),
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.SELF_LOOP_EN(SELF_LOOP_EN),
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.SELF_LOOP_EN(SELF_LOOP_EN),
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.DAw(DAw),
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.DAw(DAw),
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.CAST_TYPE(CAST_TYPE),
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.CAST_TYPE(CAST_TYPE),
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.NE(NE)
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.NE(NE)
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)
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) check_destination_addr (
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check_destination_addr(
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.dest_e_addr(dest_e_addr),
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.dest_e_addr(dest_e_addr),
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.current_e_addr(current_e_addr),
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.current_e_addr(current_e_addr),
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.dest_is_valid(valid_dst)
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.dest_is_valid(valid_dst)
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);
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);
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//assign hdr_flit_sent=pck_rd;
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//assign hdr_flit_sent=pck_rd;
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injection_ratio_ctrl # (
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injection_ratio_ctrl #
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(
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.MAX_PCK_SIZ(MAX_PCK_SIZ),
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.MAX_PCK_SIZ(MAX_PCK_SIZ),
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.MAX_RATIO(MAX_RATIO)
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.MAX_RATIO(MAX_RATIO)
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)
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) pck_inject_ratio_ctrl (
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pck_inject_ratio_ctrl
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(
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.en(inject_en),
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.en(inject_en),
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.pck_size_in(pck_size_tmp),
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.pck_size_in(pck_size_tmp),
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.freez(buffer_full),
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.freez(buffer_full),
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.inject(pck_wr),
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.inject(pck_wr),
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.ratio(ratio)
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.ratio(ratio)
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);
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);
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output_vc_status #(
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output_vc_status #(
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.CRDTw(CRDTw),
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.CRDTw(CRDTw),
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.V (V),
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.V (V),
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.B (PORT_B)
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.B (PORT_B)
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)
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) nic_ovc_status (
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nic_ovc_status
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(
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.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
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.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
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.wr_in (ovc_wr_in),
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.wr_in (ovc_wr_in),
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.credit_in (credit_in),
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.credit_in (credit_in),
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.nearly_full_vc (nearly_full_vc),
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.nearly_full_vc (nearly_full_vc),
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.full_vc (full_vc),
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.full_vc (full_vc),
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.empty_vc (empty_vc),
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.empty_vc (empty_vc),
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.cand_vc (cand_vc),
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.cand_vc (cand_vc),
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.cand_wr_vc_en (cand_wr_vc_en),
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.cand_wr_vc_en (cand_wr_vc_en),
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.clk (clk),
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.clk (clk),
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.reset (reset)
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.reset (reset)
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);
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);
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packet_gen #(
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packet_gen #(
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.P(MAX_P),
|
.NOC_ID(NOC_ID),
|
.PCK_TYPE(PCK_TYPE),
|
.P(MAX_P)
|
.ROUTE_TYPE(ROUTE_TYPE),
|
) packet_buffer (
|
.MAX_PCK_NUM(MAX_PCK_NUM),
|
|
.MAX_SIM_CLKs(MAX_SIM_CLKs),
|
|
.TIMSTMP_FIFO_NUM(TIMSTMP_FIFO_NUM),
|
|
.MIN_PCK_SIZE(MIN_PCK_SIZE),
|
|
.MAX_PCK_SIZ(MAX_PCK_SIZ)
|
|
)
|
|
packet_buffer
|
|
(
|
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.pck_wr(pck_wr),
|
.pck_wr(pck_wr),
|
.pck_rd(pck_rd),
|
.pck_rd(pck_rd),
|
.current_r_addr(current_r_addr),
|
.current_r_addr(current_r_addr),
|
.current_e_addr(current_e_addr),
|
.current_e_addr(current_e_addr),
|
.clk_counter(clk_counter+1'b1),//in case of zero load latency, the flit will be injected in the next clock cycle
|
.clk_counter(clk_counter+1'b1),//in case of zero load latency, the flit will be injected in the next clock cycle
|
.pck_number(pck_number),
|
.pck_number(pck_number),
|
.dest_e_addr_in(dest_e_addr),
|
.dest_e_addr_in(dest_e_addr),
|
.dest_e_addr_o(dest_e_addr_o),
|
.dest_e_addr_o(dest_e_addr_o),
|
.pck_timestamp(pck_timestamp),
|
.pck_timestamp(pck_timestamp),
|
.buffer_full(buffer_full),
|
.buffer_full(buffer_full),
|
.pck_ready(pck_ready),
|
.pck_ready(pck_ready),
|
.valid_dst(valid_dst),
|
.valid_dst(valid_dst),
|
.destport(destport),
|
.destport(destport),
|
.pck_size_in(pck_size_tmp),
|
.pck_size_in(pck_size_tmp),
|
.pck_size_o(pck_size)
|
.pck_size_o(pck_size)
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
assign wr_timestamp =pck_timestamp;
|
assign wr_timestamp =pck_timestamp;
|
|
|
assign update = flit_in_wr & flit_in[Fw-2];
|
assign update = flit_in_wr & flit_in[Fw-2];
|
assign hdr_flit = (flit_counter == 0);
|
assign hdr_flit = (flit_counter == 0);
|
assign tail_flit = (flit_counter == pck_size-1'b1);
|
assign tail_flit = (flit_counter == pck_size-1'b1);
|
|
|
|
|
|
|
assign time_stamp_h2h = hdr_flit_timestamp - rd_timestamp;
|
assign time_stamp_h2h = hdr_flit_timestamp - rd_timestamp;
|
assign time_stamp_h2t = clk_counter - rd_timestamp;
|
assign time_stamp_h2t = clk_counter - rd_timestamp;
|
|
|
wire [FPAYw-1 : 0] flit_out_pyload;
|
wire [FPAYw-1 : 0] flit_out_pyload;
|
wire [1 : 0] flit_out_hdr;
|
wire [1 : 0] flit_out_hdr;
|
|
|
|
|
wire [FPAYw-1 : 0] flit_out_header_pyload;
|
wire [FPAYw-1 : 0] flit_out_header_pyload;
|
wire [Fw-1 : 0] hdr_flit_out;
|
wire [Fw-1 : 0] hdr_flit_out;
|
|
|
|
|
|
|
|
|
|
|
assign hdr_data_in = (MIN_PCK_SIZE==1)? wr_timestamp[HDR_Dw-1 : 0] : {HDR_Dw{1'b0}};
|
assign hdr_data_in = (MIN_PCK_SIZE==1)? wr_timestamp[HDR_Dw-1 : 0] : {HDR_Dw{1'b0}};
|
|
|
header_flit_generator #(
|
header_flit_generator #(
|
|
.NOC_ID(NOC_ID),
|
.DATA_w(HDR_DATA_w)
|
.DATA_w(HDR_DATA_w)
|
)
|
) the_header_flit_generator (
|
the_header_flit_generator
|
|
(
|
|
.flit_out(hdr_flit_out),
|
.flit_out(hdr_flit_out),
|
.vc_num_in(wr_vc),
|
.vc_num_in(wr_vc),
|
.class_in(pck_class_in),
|
.class_in(pck_class_in),
|
.dest_e_addr_in(dest_e_addr_o),
|
.dest_e_addr_in(dest_e_addr_o),
|
.src_e_addr_in(current_e_addr),
|
.src_e_addr_in(current_e_addr),
|
.weight_in(init_weight),
|
.weight_in(init_weight),
|
.destport_in(destport),
|
.destport_in(destport),
|
.data_in(hdr_data_in),
|
.data_in(hdr_data_in),
|
.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
|
.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
|
);
|
);
|
|
|
assign flit_out_class = pck_class_in;
|
assign flit_out_class = pck_class_in;
|
|
|
assign flit_out_hdr = {hdr_flit,tail_flit};
|
assign flit_out_hdr = {hdr_flit,tail_flit};
|
|
|
assign flit_out_header_pyload = hdr_flit_out[FPAYw-1 : 0];
|
assign flit_out_header_pyload = hdr_flit_out[FPAYw-1 : 0];
|
|
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
assign flit_out_pyload = (hdr_flit) ? flit_out_header_pyload :
|
assign flit_out_pyload = (hdr_flit) ? flit_out_header_pyload :
|
|
|
(tail_flit) ? wr_timestamp:
|
(tail_flit) ? wr_timestamp:
|
{pck_number,flit_counter};
|
{pck_number,flit_counter};
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
|
|
|
|
assign flit_out = {flit_out_hdr, wr_vc, flit_out_pyload };
|
assign flit_out = {flit_out_hdr, wr_vc, flit_out_pyload };
|
|
|
|
|
//extract header flit info
|
//extract header flit info
|
|
|
|
|
|
|
extract_header_flit_info #(
|
extract_header_flit_info #(
|
|
.NOC_ID(NOC_ID),
|
.DATA_w(HDR_DATA_w)
|
.DATA_w(HDR_DATA_w)
|
)
|
) header_extractor (
|
header_extractor
|
|
(
|
|
.flit_in(flit_in),
|
.flit_in(flit_in),
|
.flit_in_wr(flit_in_wr),
|
.flit_in_wr(flit_in_wr),
|
.class_o(rd_class_hdr),
|
.class_o(rd_class_hdr),
|
.destport_o(),
|
.destport_o(),
|
.dest_e_addr_o(rd_des_e_addr),
|
.dest_e_addr_o(rd_des_e_addr),
|
.src_e_addr_o(rd_src_e_addr),
|
.src_e_addr_o(rd_src_e_addr),
|
.vc_num_o(rd_vc),
|
.vc_num_o(rd_vc),
|
.hdr_flit_wr_o( ),
|
.hdr_flit_wr_o( ),
|
.hdr_flg_o(rd_hdr_flg),
|
.hdr_flg_o(rd_hdr_flg),
|
.tail_flg_o(rd_tail_flg),
|
.tail_flg_o(rd_tail_flg),
|
.weight_o( ),
|
.weight_o( ),
|
.be_o( ),
|
.be_o( ),
|
.data_o(rd_hdr_data_out)
|
.data_o(rd_hdr_data_out)
|
);
|
);
|
|
|
|
|
distance_gen #(
|
distance_gen #(
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.EAw(EAw),
|
.EAw(EAw),
|
.DISTw(DISTw)
|
.DISTw(DISTw)
|
)
|
) the_distance_gen (
|
the_distance_gen
|
|
(
|
|
.src_e_addr(src_e_addr),
|
.src_e_addr(src_e_addr),
|
.dest_e_addr(current_e_addr),
|
.dest_e_addr(current_e_addr),
|
.distance(distance)
|
.distance(distance)
|
);
|
);
|
|
|
|
|
generate
|
generate
|
if(MIN_PCK_SIZE == 1) begin : sf_pck
|
if(MIN_PCK_SIZE == 1) begin : sf_pck
|
assign src_e_addr = (rd_hdr_flg & rd_tail_flg)? rd_src_e_addr : rsv_pck_src_e_addr[rd_vc_bin];
|
assign src_e_addr = (rd_hdr_flg & rd_tail_flg)? rd_src_e_addr : rsv_pck_src_e_addr[rd_vc_bin];
|
assign pck_class_out = (rd_hdr_flg & rd_tail_flg)? rd_class_hdr : rsv_pck_class_in[rd_vc_bin];
|
assign pck_class_out = (rd_hdr_flg & rd_tail_flg)? rd_class_hdr : rsv_pck_class_in[rd_vc_bin];
|
assign hdr_flit_timestamp = (rd_hdr_flg & rd_tail_flg)? clk_counter : rsv_time_stamp[rd_vc_bin];
|
assign hdr_flit_timestamp = (rd_hdr_flg & rd_tail_flg)? clk_counter : rsv_time_stamp[rd_vc_bin];
|
assign rd_timestamp = (rd_hdr_flg & rd_tail_flg)? rd_hdr_data_out : flit_in[CLK_CNTw-1 : 0];
|
assign rd_timestamp = (rd_hdr_flg & rd_tail_flg)? rd_hdr_data_out : flit_in[CLK_CNTw-1 : 0];
|
assign pck_size_o = (rd_hdr_flg & rd_tail_flg)? 1 : rsv_pck_size[rd_vc_bin];
|
assign pck_size_o = (rd_hdr_flg & rd_tail_flg)? 1 : rsv_pck_size[rd_vc_bin];
|
end else begin : no_sf_pck
|
end else begin : no_sf_pck
|
assign pck_size_o = rsv_pck_size[rd_vc_bin];
|
assign pck_size_o = rsv_pck_size[rd_vc_bin];
|
assign src_e_addr = rsv_pck_src_e_addr[rd_vc_bin];
|
assign src_e_addr = rsv_pck_src_e_addr[rd_vc_bin];
|
assign pck_class_out = rsv_pck_class_in[rd_vc_bin];
|
assign pck_class_out = rsv_pck_class_in[rd_vc_bin];
|
assign hdr_flit_timestamp = rsv_time_stamp[rd_vc_bin];
|
assign hdr_flit_timestamp = rsv_time_stamp[rd_vc_bin];
|
assign rd_timestamp=flit_in[CLK_CNTw-1 : 0];
|
assign rd_timestamp=flit_in[CLK_CNTw-1 : 0];
|
end
|
end
|
|
|
|
|
if(V==1) begin : v1
|
if(V==1) begin : v1
|
assign rd_vc_bin=1'b0;
|
assign rd_vc_bin=1'b0;
|
// assign wr_vc_bin=1'b0;
|
// assign wr_vc_bin=1'b0;
|
end else begin :vother
|
end else begin :vother
|
|
|
one_hot_to_bin #( .ONE_HOT_WIDTH (V)) conv1
|
one_hot_to_bin #( .ONE_HOT_WIDTH (V)) conv1
|
(
|
(
|
.one_hot_code (rd_vc),
|
.one_hot_code (rd_vc),
|
.bin_code (rd_vc_bin)
|
.bin_code (rd_vc_bin)
|
);
|
);
|
/*
|
/*
|
one_hot_to_bin #( .ONE_HOT_WIDTH (V)) conv2
|
one_hot_to_bin #( .ONE_HOT_WIDTH (V)) conv2
|
(
|
(
|
.one_hot_code (wr_vc),
|
.one_hot_code (wr_vc),
|
.bin_code (wr_vc_bin)
|
.bin_code (wr_vc_bin)
|
);
|
);
|
*/
|
*/
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
assign ovc_wr_in = (flit_out_wr ) ? wr_vc : {V{1'b0}};
|
assign ovc_wr_in = (flit_out_wr ) ? wr_vc : {V{1'b0}};
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
assign wr_vc_is_full = (SSA_EN=="NO")? | ( full_vc & wr_vc) : | (nearly_full_vc & wr_vc);
|
//assign wr_vc_is_full = (SSA_EN=="NO")? | ( full_vc & wr_vc) : | (nearly_full_vc & wr_vc);
|
|
assign wr_vc_is_full = | ( full_vc & wr_vc);
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
|
|
generate
|
generate
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(VC_REALLOCATION_TYPE == "NONATOMIC") begin : nanatom_b
|
if(VC_REALLOCATION_TYPE == "NONATOMIC") begin : nanatom_b
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
assign wr_vc_avb = ~wr_vc_is_full;
|
assign wr_vc_avb = ~wr_vc_is_full;
|
end else begin : atomic_b
|
end else begin : atomic_b
|
assign wr_vc_is_empty = | ( empty_vc & wr_vc);
|
assign wr_vc_is_empty = | ( empty_vc & wr_vc);
|
assign wr_vc_avb = wr_vc_is_empty;
|
assign wr_vc_avb = wr_vc_is_empty;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
reg not_yet_sent_aflit_next,not_yet_sent_aflit;
|
reg not_yet_sent_aflit_next,not_yet_sent_aflit;
|
|
|
always @(*)begin
|
always @(*)begin
|
wr_vc_next = wr_vc;
|
wr_vc_next = wr_vc;
|
cand_wr_vc_en = 1'b0;
|
cand_wr_vc_en = 1'b0;
|
flit_out_wr = 1'b0;
|
flit_out_wr = 1'b0;
|
flit_cnt_inc = 1'b0;
|
flit_cnt_inc = 1'b0;
|
flit_cnt_rst = 1'b0;
|
flit_cnt_rst = 1'b0;
|
credit_out_next = {V{1'd0}};
|
credit_out_next = {V{1'd0}};
|
sent_done = 1'b0;
|
sent_done = 1'b0;
|
pck_rd = 1'b0;
|
pck_rd = 1'b0;
|
hdr_flit_sent =1'b0;
|
hdr_flit_sent =1'b0;
|
ns = ps;
|
ns = ps;
|
pck_rd =1'b0;
|
pck_rd =1'b0;
|
|
|
|
|
not_yet_sent_aflit_next =not_yet_sent_aflit;
|
not_yet_sent_aflit_next =not_yet_sent_aflit;
|
case (ps)
|
case (ps)
|
IDEAL: begin
|
IDEAL: begin
|
if(pck_ready ) begin
|
if(pck_ready ) begin
|
if(wr_vc_avb && valid_dst)begin
|
if(wr_vc_avb && valid_dst)begin
|
|
|
hdr_flit_sent=1'b1;
|
hdr_flit_sent=1'b1;
|
flit_out_wr = 1'b1;//sending header flit
|
flit_out_wr = 1'b1;//sending header flit
|
not_yet_sent_aflit_next = 1'b0;
|
not_yet_sent_aflit_next = 1'b0;
|
flit_cnt_inc = 1'b1;
|
flit_cnt_inc = 1'b1;
|
if (MIN_PCK_SIZE>1 || flit_out_hdr!=2'b11) begin
|
if (MIN_PCK_SIZE>1 || flit_out_hdr!=2'b11) begin
|
ns = SENT;
|
ns = SENT;
|
end else begin
|
end else begin
|
pck_rd=1'b1;
|
pck_rd=1'b1;
|
flit_cnt_rst = 1'b1;
|
flit_cnt_rst = 1'b1;
|
sent_done =1'b1;
|
sent_done =1'b1;
|
cand_wr_vc_en =1'b1;
|
cand_wr_vc_en =1'b1;
|
if(cand_vc>0) begin
|
if(cand_vc>0) begin
|
wr_vc_next = cand_vc;
|
wr_vc_next = cand_vc;
|
end else ns = WAIT;
|
end else ns = WAIT;
|
end //else
|
end //else
|
end//wr_vc
|
end//wr_vc
|
end
|
end
|
|
|
end //IDEAL
|
end //IDEAL
|
SENT: begin
|
SENT: begin
|
|
|
if(!wr_vc_is_full )begin
|
if(!wr_vc_is_full )begin
|
|
|
flit_out_wr = 1'b1;
|
flit_out_wr = 1'b1;
|
if(flit_counter < pck_size-1) begin
|
if(flit_counter < pck_size-1) begin
|
flit_cnt_inc = 1'b1;
|
flit_cnt_inc = 1'b1;
|
end else begin
|
end else begin
|
flit_cnt_rst = 1'b1;
|
flit_cnt_rst = 1'b1;
|
sent_done =1'b1;
|
sent_done =1'b1;
|
pck_rd=1'b1;
|
pck_rd=1'b1;
|
cand_wr_vc_en =1'b1;
|
cand_wr_vc_en =1'b1;
|
if(cand_vc>0) begin
|
if(cand_vc>0) begin
|
wr_vc_next = cand_vc;
|
wr_vc_next = cand_vc;
|
ns =IDEAL;
|
ns =IDEAL;
|
end else ns = WAIT;
|
end else ns = WAIT;
|
end//else
|
end//else
|
end // if wr_vc_is_full
|
end // if wr_vc_is_full
|
end//SENT
|
end//SENT
|
WAIT:begin
|
WAIT:begin
|
|
|
cand_wr_vc_en =1'b1;
|
cand_wr_vc_en =1'b1;
|
if(cand_vc>0) begin
|
if(cand_vc>0) begin
|
wr_vc_next = cand_vc;
|
wr_vc_next = cand_vc;
|
ns =IDEAL;
|
ns =IDEAL;
|
end
|
end
|
end
|
end
|
default: begin
|
default: begin
|
ns =IDEAL;
|
ns =IDEAL;
|
end
|
end
|
endcase
|
endcase
|
|
|
|
|
// packet sink
|
// packet sink
|
if(flit_in_wr) begin
|
if(flit_in_wr) begin
|
credit_out_next = rd_vc;
|
credit_out_next = rd_vc;
|
end else credit_out_next = {V{1'd0}};
|
end else credit_out_next = {V{1'd0}};
|
end
|
end
|
|
|
|
|
always @ (`pronoc_clk_reset_edge )begin
|
always @ (`pronoc_clk_reset_edge )begin
|
if(`pronoc_reset) begin
|
if(`pronoc_reset) begin
|
inject_en <= 1'b0;
|
inject_en <= 1'b0;
|
ps <= IDEAL;
|
ps <= IDEAL;
|
wr_vc <=1;
|
wr_vc <=1;
|
flit_counter <= {PCK_SIZw{1'b0}};
|
flit_counter <= {PCK_SIZw{1'b0}};
|
credit_out <= {V{1'd0}};
|
credit_out <= {V{1'd0}};
|
rsv_counter <= 0;
|
rsv_counter <= 0;
|
clk_counter <= 0;
|
clk_counter <= 0;
|
not_yet_sent_aflit<=1'b1;
|
not_yet_sent_aflit<=1'b1;
|
|
|
end else begin
|
end else begin
|
//injection
|
//injection
|
not_yet_sent_aflit<=not_yet_sent_aflit_next;
|
not_yet_sent_aflit<=not_yet_sent_aflit_next;
|
inject_en <= (start_injection |inject_en) & ~stop;
|
inject_en <= (start_injection |inject_en) & ~stop;
|
ps <= ns;
|
ps <= ns;
|
clk_counter <= clk_counter+1'b1;
|
clk_counter <= clk_counter+1'b1;
|
wr_vc <=wr_vc_next;
|
wr_vc <=wr_vc_next;
|
if (flit_cnt_rst) flit_counter <= {PCK_SIZw{1'b0}};
|
if (flit_cnt_rst) flit_counter <= {PCK_SIZw{1'b0}};
|
else if(flit_cnt_inc) flit_counter <= flit_counter + 1'b1;
|
else if(flit_cnt_inc) flit_counter <= flit_counter + 1'b1;
|
credit_out <= credit_out_next;
|
credit_out <= credit_out_next;
|
|
|
|
|
//sink
|
//sink
|
if(flit_in_wr) begin
|
if(flit_in_wr) begin
|
if (flit_in[Fw-1])begin //header flit
|
if (flit_in[Fw-1])begin //header flit
|
rsv_pck_src_e_addr[rd_vc_bin] <= rd_src_e_addr;
|
rsv_pck_src_e_addr[rd_vc_bin] <= rd_src_e_addr;
|
rsv_pck_class_in[rd_vc_bin] <= rd_class_hdr;
|
rsv_pck_class_in[rd_vc_bin] <= rd_class_hdr;
|
rsv_time_stamp[rd_vc_bin] <= clk_counter;
|
rsv_time_stamp[rd_vc_bin] <= clk_counter;
|
rsv_counter <= rsv_counter+1'b1;
|
rsv_counter <= rsv_counter+1'b1;
|
rsv_pck_size[rd_vc_bin] <=2;
|
rsv_pck_size[rd_vc_bin] <=2;
|
// distance <= {{(32-8){1'b0}},flit_in[7:0]};
|
// distance <= {{(32-8){1'b0}},flit_in[7:0]};
|
`ifdef RSV_NOTIFICATION
|
`ifdef RSV_NOTIFICATION
|
// synopsys translate_off
|
// synopsys translate_off
|
// synthesis translate_off
|
// synthesis translate_off
|
// last_pck_time<=$time;
|
// last_pck_time<=$time;
|
$display ("total of %d pcks have been recived in core (%d)", rsv_counter,current_e_addr);
|
$display ("total of %d pcks have been recived in core (%d)", rsv_counter,current_e_addr);
|
// synthesis translate_on
|
// synthesis translate_on
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
end else begin
|
end else begin
|
rsv_pck_size[rd_vc_bin] <=rsv_pck_size[rd_vc_bin]+1;
|
rsv_pck_size[rd_vc_bin] <=rsv_pck_size[rd_vc_bin]+1;
|
end
|
end
|
end
|
end
|
// synopsys translate_off
|
// synopsys translate_off
|
// synthesis translate_off
|
// synthesis translate_off
|
if(report) begin
|
if(report) begin
|
$display ("%t,\t total of %d pcks have been recived in core (%d)",$time ,rsv_counter,current_e_addr);
|
$display ("%t,\t total of %d pcks have been recived in core (%d)",$time ,rsv_counter,current_e_addr);
|
end
|
end
|
// synthesis translate_on
|
// synthesis translate_on
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
|
|
|
|
|
|
|
|
end
|
end
|
end//always
|
end//always
|
|
|
|
|
|
|
|
|
|
|
|
|
wire [NE-1 :0] dest_mcast_all_endp1;
|
wire [NE-1 :0] dest_mcast_all_endp1;
|
|
|
|
|
generate
|
generate
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(CAST_TYPE != "UNICAST") begin :mb_cast
|
if(CAST_TYPE != "UNICAST") begin :mb_cast
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
wire [NEw-1 : 0] sum_temp;
|
wire [NEw-1 : 0] sum_temp;
|
wire is_unicast;
|
wire is_unicast;
|
|
|
mcast_dest_list_decode decode1 (
|
mcast_dest_list_decode #(
|
|
.NOC_ID(NOC_ID)
|
|
) decode1 (
|
.dest_e_addr(dest_e_addr_o),
|
.dest_e_addr(dest_e_addr_o),
|
.dest_o(dest_mcast_all_endp1),
|
.dest_o(dest_mcast_all_endp1),
|
.row_has_any_dest(),
|
.row_has_any_dest(),
|
.is_unicast(is_unicast)
|
.is_unicast(is_unicast)
|
);
|
);
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if (CAST_TYPE == "BROADCAST_FULL") begin :bcastf
|
if (CAST_TYPE == "BROADCAST_FULL") begin :bcastf
|
assign mcast_dst_num_o = (is_unicast) ? 1 : (SELF_LOOP_EN == "NO")? NE-1 : NE;
|
assign mcast_dst_num_o = (is_unicast) ? 1 : (SELF_LOOP_EN == "NO")? NE-1 : NE;
|
end else if ( CAST_TYPE == "BROADCAST_PARTIAL" ) begin :bcastp
|
end else if ( CAST_TYPE == "BROADCAST_PARTIAL" ) begin :bcastp
|
|
|
if (SELF_LOOP_EN == "NO") begin
|
if (SELF_LOOP_EN == "NO") begin
|
//check if injector node is included in partial list
|
//check if injector node is included in partial list
|
wire [NEw-1: 0] current_enp_id;
|
wire [NEw-1: 0] current_enp_id;
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod1 ( .id(current_enp_id), .code(current_e_addr));
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod1 ( .id(current_enp_id), .code(current_e_addr));
|
assign mcast_dst_num_o = (is_unicast) ? 1 : (MCAST_ENDP_LIST[current_enp_id]== 1'b1)? MCAST_PRTLw-1 : MCAST_PRTLw;
|
assign mcast_dst_num_o = (is_unicast) ? 1 : (MCAST_ENDP_LIST[current_enp_id]== 1'b1)? MCAST_PRTLw-1 : MCAST_PRTLw;
|
|
|
end else begin
|
end else begin
|
assign mcast_dst_num_o = (is_unicast)? 1 : MCAST_PRTLw;
|
assign mcast_dst_num_o = (is_unicast)? 1 : MCAST_PRTLw;
|
end
|
end
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
end else begin : mcast
|
end else begin : mcast
|
accumulator #(
|
accumulator #(
|
.INw(NE),
|
.INw(NE),
|
.OUTw(NEw),
|
.OUTw(NEw),
|
.NUM(NE)
|
.NUM(NE)
|
)accum
|
)accum
|
(
|
(
|
.in_all(dest_mcast_all_endp1),
|
.in_all(dest_mcast_all_endp1),
|
.out(sum_temp)
|
.out(sum_temp)
|
);
|
);
|
assign mcast_dst_num_o = sum_temp;
|
assign mcast_dst_num_o = sum_temp;
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
|
|
|
|
/***************************************************************
|
/***************************************************************
|
* simulation code
|
* simulation code
|
* ************************************************************/
|
* ************************************************************/
|
|
|
|
|
|
|
|
|
|
|
// synthesis translate_off
|
// synthesis translate_off
|
|
|
wire [NEw-1: 0] src_id,dst_id,current_id;
|
wire [NEw-1: 0] src_id,dst_id,current_id;
|
|
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod1 ( .id(current_id), .code(current_e_addr));
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod1 ( .id(current_id), .code(current_e_addr));
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod2 ( .id(dst_id), .code(rd_des_e_addr[EAw-1 : 0]));// only for unicast
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod2 ( .id(dst_id), .code(rd_des_e_addr[EAw-1 : 0]));// only for unicast
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod3 ( .id(src_id), .code(rd_src_e_addr));
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod3 ( .id(src_id), .code(rd_src_e_addr));
|
|
|
|
|
|
|
|
|
|
|
wire [NE-1 :0] dest_mcast_all_endp2;
|
wire [NE-1 :0] dest_mcast_all_endp2;
|
generate
|
generate
|
if(CAST_TYPE != "UNICAST") begin :no_unicast
|
if(CAST_TYPE != "UNICAST") begin :no_unicast
|
mcast_dest_list_decode decode2 (
|
mcast_dest_list_decode #(
|
|
.NOC_ID(NOC_ID)
|
|
) decode2 (
|
.dest_e_addr(rd_des_e_addr),
|
.dest_e_addr(rd_des_e_addr),
|
.dest_o(dest_mcast_all_endp2),
|
.dest_o(dest_mcast_all_endp2),
|
.row_has_any_dest(),
|
.row_has_any_dest(),
|
.is_unicast()
|
.is_unicast()
|
);
|
);
|
end endgenerate
|
end
|
|
endgenerate
|
|
|
|
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(CAST_TYPE == "UNICAST") begin
|
if(CAST_TYPE == "UNICAST") begin
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
if(flit_out_wr && hdr_flit && dest_e_addr_o [EAw-1 : 0] == current_e_addr && SELF_LOOP_EN == "NO") begin
|
if(flit_out_wr && hdr_flit && dest_e_addr_o [EAw-1 : 0] == current_e_addr && SELF_LOOP_EN == "NO") begin
|
$display("%t: ERROR: The self-loop is not enabled in the router while a packet is injected to the NoC with identical source and destination address in endpoint (%h).: %m",$time, dest_e_addr_o );
|
$display("%t: ERROR: The self-loop is not enabled in the router while a packet is injected to the NoC with identical source and destination address in endpoint (%h).: %m",$time, dest_e_addr_o );
|
$finish;
|
$finish;
|
end
|
end
|
if(flit_in_wr && rd_hdr_flg && (rd_des_e_addr[EAw-1 : 0] != current_e_addr )) begin
|
if(flit_in_wr && rd_hdr_flg && (rd_des_e_addr[EAw-1 : 0] != current_e_addr )) begin
|
$display("%t: ERROR: packet with destination %d (code %h) which is sent by source %d (code %h) has been recieved in wrong destination %d (code %h). %m",$time,dst_id,rd_des_e_addr, src_id,rd_src_e_addr, current_id,current_e_addr);
|
$display("%t: ERROR: packet with destination %d (code %h) which is sent by source %d (code %h) has been recieved in wrong destination %d (code %h). %m",$time,dst_id,rd_des_e_addr, src_id,rd_src_e_addr, current_id,current_e_addr);
|
$finish;
|
$finish;
|
end
|
end
|
|
|
end else begin
|
end else begin
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if((CAST_TYPE == "MULTICAST_FULL") || (CAST_TYPE == "MULTICAST_PARTIAL")) begin
|
if((CAST_TYPE == "MULTICAST_FULL") || (CAST_TYPE == "MULTICAST_PARTIAL")) begin
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
if(flit_out_wr && hdr_flit && dest_mcast_all_endp1[current_id] == 1'b1 && SELF_LOOP_EN == "NO") begin
|
if(flit_out_wr && hdr_flit && dest_mcast_all_endp1[current_id] == 1'b1 && SELF_LOOP_EN == "NO") begin
|
$display("%t: ERROR: The self-loop is not enabled in the router while a packet is injected to the NoC with identical source and destination address in endpoint %d. destination nodes:0X%h. : %m",$time, current_id,dest_mcast_all_endp1 );
|
$display("%t: ERROR: The self-loop is not enabled in the router while a packet is injected to the NoC with identical source and destination address in endpoint %d. destination nodes:0X%h. : %m",$time, current_id,dest_mcast_all_endp1 );
|
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
if(flit_in_wr && rd_hdr_flg && (dest_mcast_all_endp2[current_id] !=1'b1 )) begin
|
if(flit_in_wr && rd_hdr_flg && (dest_mcast_all_endp2[current_id] !=1'b1 )) begin
|
$display("%t: ERROR: packet with destination %b which is sent by source %d (code %h) has been recieved in wrong destination %d (code %h). %m",$time, dest_mcast_all_endp2, src_id,rd_src_e_addr, current_id,current_e_addr);
|
$display("%t: ERROR: packet with destination %b which is sent by source %d (code %h) has been recieved in wrong destination %d (code %h). %m",$time, dest_mcast_all_endp2, src_id,rd_src_e_addr, current_id,current_e_addr);
|
$finish;
|
$finish;
|
end
|
end
|
|
|
//check multicast packet size to be smaller than B & LB
|
//check multicast packet size to be smaller than B & LB
|
if(flit_out_wr & hdr_flit & (mcast_dst_num_o>1) & (pck_size >B || pck_size> LB))begin
|
if(flit_out_wr & hdr_flit & (mcast_dst_num_o>1) & (pck_size >B || pck_size> LB))begin
|
$display("%t: ERROR: A multicast packat is injected to the NoC which has larger size (%d) than router buffer width. %m",$time, pck_size);
|
$display("%t: ERROR: A multicast packat is injected to the NoC which has larger size (%d) than router buffer width. %m",$time, pck_size);
|
$finish;
|
$finish;
|
end
|
end
|
|
|
end
|
end
|
if(update) begin
|
if(update) begin
|
if (hdr_flit_timestamp<= rd_timestamp) begin
|
if (hdr_flit_timestamp<= rd_timestamp) begin
|
$display("%t: ERROR: In destination %d packt which is sent by source %d, the time when header flit is recived (%d) should be larger than the packet timestamp %d. %m",$time, current_id ,src_e_addr, hdr_flit_timestamp, rd_timestamp);
|
$display("%t: ERROR: In destination %d packt which is sent by source %d, the time when header flit is recived (%d) should be larger than the packet timestamp %d. %m",$time, current_id ,src_e_addr, hdr_flit_timestamp, rd_timestamp);
|
$finish;
|
$finish;
|
end
|
end
|
if( clk_counter <= rd_timestamp) begin
|
if( clk_counter <= rd_timestamp) begin
|
$display("%t: ERROR: ERROR: In destination %d packt which is sent by source %d,, the current time (%d) should be larger than the packet timestamp %d. %m",$time, current_id ,src_e_addr, clk_counter, rd_timestamp);
|
$display("%t: ERROR: ERROR: In destination %d packt which is sent by source %d,, the current time (%d) should be larger than the packet timestamp %d. %m",$time, current_id ,src_e_addr, clk_counter, rd_timestamp);
|
$finish;
|
$finish;
|
end
|
end
|
end//update
|
end//update
|
if(tail_flit & flit_out_wr) begin
|
if(tail_flit & flit_out_wr) begin
|
if(wr_timestamp > clk_counter) begin
|
if(wr_timestamp > clk_counter) begin
|
$display("%t: ERROR: In src %d, the current time (%d) should be larger than or equal to the packet timestamp %d. %m",$time, current_id, clk_counter, wr_timestamp);
|
$display("%t: ERROR: In src %d, the current time (%d) should be larger than or equal to the packet timestamp %d. %m",$time, current_id, clk_counter, wr_timestamp);
|
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
`ifdef CHECK_PCKS_CONTENT
|
`ifdef CHECK_PCKS_CONTENT
|
|
|
|
|
wire [PCK_SIZw-1 : 0] rsv_flit_counter;
|
wire [PCK_SIZw-1 : 0] rsv_flit_counter;
|
reg [PCK_SIZw-1 : 0] old_flit_counter [V-1 : 0];
|
reg [PCK_SIZw-1 : 0] old_flit_counter [V-1 : 0];
|
wire [PCK_CNTw-1 : 0] rsv_pck_number;
|
wire [PCK_CNTw-1 : 0] rsv_pck_number;
|
reg [PCK_CNTw-1 : 0] old_pck_number [V-1 : 0];
|
reg [PCK_CNTw-1 : 0] old_pck_number [V-1 : 0];
|
|
|
wire [PCK_CNTw+PCK_SIZw-1 : 0] statistics;
|
wire [PCK_CNTw+PCK_SIZw-1 : 0] statistics;
|
generate
|
generate
|
if(PCK_CNTw+PCK_SIZw > Fw) assign statistics = {{(PCK_CNTw+PCK_SIZw-Fw){1'b0}},flit_in};
|
if(PCK_CNTw+PCK_SIZw > Fw) assign statistics = {{(PCK_CNTw+PCK_SIZw-Fw){1'b0}},flit_in};
|
else assign statistics = flit_in[PCK_CNTw+PCK_SIZw-1 : 0];
|
else assign statistics = flit_in[PCK_CNTw+PCK_SIZw-1 : 0];
|
assign {rsv_pck_number,rsv_flit_counter}=statistics;
|
assign {rsv_pck_number,rsv_flit_counter}=statistics;
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
integer ii;
|
integer ii;
|
|
|
always @ (`pronoc_clk_reset_edge )begin
|
always @ (`pronoc_clk_reset_edge )begin
|
if(`pronoc_reset) begin
|
if(`pronoc_reset) begin
|
for(ii=0;ii
|
for(ii=0;ii
|
old_flit_counter[ii]<=0;
|
old_flit_counter[ii]<=0;
|
end
|
end
|
end else begin
|
end else begin
|
if(flit_in_wr)begin
|
if(flit_in_wr)begin
|
if ( flit_in[Fw-1:Fw-2]==2'b10) begin
|
if ( flit_in[Fw-1:Fw-2]==2'b10) begin
|
old_pck_number[rd_vc_bin]<=0;
|
old_pck_number[rd_vc_bin]<=0;
|
old_flit_counter[rd_vc_bin]<=0;
|
old_flit_counter[rd_vc_bin]<=0;
|
end else if ( flit_in[Fw-1:Fw-2]==2'b00)begin
|
end else if ( flit_in[Fw-1:Fw-2]==2'b00)begin
|
old_pck_number[rd_vc_bin]<=rsv_pck_number;
|
old_pck_number[rd_vc_bin]<=rsv_pck_number;
|
old_flit_counter[rd_vc_bin]<=rsv_flit_counter;
|
old_flit_counter[rd_vc_bin]<=rsv_flit_counter;
|
end
|
end
|
|
|
end //flit_in_wr
|
end //flit_in_wr
|
|
|
end //reset
|
end //reset
|
end//always
|
end//always
|
|
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if(flit_in_wr && (flit_in[Fw-1:Fw-2]==2'b00) && (~reset))begin
|
if(flit_in_wr && (flit_in[Fw-1:Fw-2]==2'b00) && (~reset))begin
|
if( old_flit_counter[rd_vc_bin]!=rsv_flit_counter-1) $display("%t: Error: missmatch flit counter in %m. Expected %d but recieved %d",$time,old_flit_counter[rd_vc_bin]+1,rsv_flit_counter);
|
if( old_flit_counter[rd_vc_bin]!=rsv_flit_counter-1) $display("%t: Error: missmatch flit counter in %m. Expected %d but recieved %d",$time,old_flit_counter[rd_vc_bin]+1,rsv_flit_counter);
|
if( old_pck_number[rd_vc_bin]!=rsv_pck_number && old_pck_number[rd_vc_bin]!=0) $display("%t: Error: missmatch pck number in %m. expected %d but recieved %d",$time,old_pck_number[rd_vc_bin],rsv_pck_number);
|
if( old_pck_number[rd_vc_bin]!=rsv_pck_number && old_pck_number[rd_vc_bin]!=0) $display("%t: Error: missmatch pck number in %m. expected %d but recieved %d",$time,old_pck_number[rd_vc_bin],rsv_pck_number);
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
`endif
|
`endif
|
|
|
// synthesis translate_on
|
// synthesis translate_on
|
|
|
|
|
|
|
|
|
|
|
// `ifdef VERILATOR
|
// `ifdef VERILATOR
|
// logic endp_is_active /*verilator public_flat_rd*/ ;
|
// logic endp_is_active /*verilator public_flat_rd*/ ;
|
//
|
//
|
// always @ (*) begin
|
// always @ (*) begin
|
// endp_is_active = 1'b0;
|
// endp_is_active = 1'b0;
|
// if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
|
// if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
|
// if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
|
// if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
|
// if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
|
// if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
|
// end
|
// end
|
// `endif
|
// `endif
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
/*****************************
|
/*****************************
|
injection_ratio_ctrl
|
injection_ratio_ctrl
|
|
|
*****************************/
|
*****************************/
|
module injection_ratio_ctrl #
|
module injection_ratio_ctrl #
|
(
|
(
|
parameter MAX_PCK_SIZ=10,
|
parameter MAX_PCK_SIZ=10,
|
parameter MAX_RATIO=100
|
parameter MAX_RATIO=100
|
)(
|
)(
|
en,
|
en,
|
pck_size_in, // average packet size in flit x10
|
pck_size_in, // average packet size in flit x10
|
clk,
|
clk,
|
reset,
|
reset,
|
inject,// inject one packet
|
inject,// inject one packet
|
freez,
|
freez,
|
ratio // 0~100 flit injection ratio
|
ratio // 0~100 flit injection ratio
|
);
|
);
|
|
|
|
|
function integer log2;
|
function integer log2;
|
input integer number; begin
|
input integer number; begin
|
log2=(number <=1) ? 1: 0;
|
log2=(number <=1) ? 1: 0;
|
while(2**log2
|
while(2**log2
|
log2=log2+1;
|
log2=log2+1;
|
end
|
end
|
end
|
end
|
endfunction // log2
|
endfunction // log2
|
|
|
|
|
localparam PCK_SIZw= log2(MAX_PCK_SIZ);
|
localparam PCK_SIZw= log2(MAX_PCK_SIZ);
|
|
|
|
|
localparam CNTw = log2(MAX_RATIO);
|
localparam CNTw = log2(MAX_RATIO);
|
localparam STATE_INIT= MAX_PCK_SIZ*MAX_RATIO;
|
localparam STATE_INIT= MAX_PCK_SIZ*MAX_RATIO;
|
localparam STATEw = log2(MAX_PCK_SIZ*2*MAX_RATIO);
|
localparam STATEw = log2(MAX_PCK_SIZ*2*MAX_RATIO);
|
|
|
input clk,reset,freez,en;
|
input clk,reset,freez,en;
|
output reg inject;
|
output reg inject;
|
input [CNTw-1 : 0] ratio;
|
input [CNTw-1 : 0] ratio;
|
input [PCK_SIZw-1 :0] pck_size_in;
|
input [PCK_SIZw-1 :0] pck_size_in;
|
reg [PCK_SIZw-1 :0]pck_size;
|
reg [PCK_SIZw-1 :0]pck_size;
|
|
|
wire [CNTw-1 : 0] on_clks, off_clks;
|
wire [CNTw-1 : 0] on_clks, off_clks;
|
reg [STATEw-1 : 0] state,next_state;
|
reg [STATEw-1 : 0] state,next_state;
|
wire input_changed;
|
wire input_changed;
|
reg [CNTw-1 : 0] ratio_old;
|
reg [CNTw-1 : 0] ratio_old;
|
|
|
always @(posedge clk ) ratio_old<=ratio;
|
always @(posedge clk ) ratio_old<=ratio;
|
|
|
assign input_changed = (ratio_old!=ratio);
|
assign input_changed = (ratio_old!=ratio);
|
|
|
|
|
assign on_clks = ratio;
|
assign on_clks = ratio;
|
assign off_clks =MAX_RATIO-ratio;
|
assign off_clks =MAX_RATIO-ratio;
|
|
|
reg [PCK_SIZw-1 :0] flit_counter,next_flit_counter;
|
reg [PCK_SIZw-1 :0] flit_counter,next_flit_counter;
|
|
|
|
|
reg sent,next_sent,next_inject;
|
reg sent,next_sent,next_inject;
|
|
|
|
|
|
|
always @(*) begin
|
always @(*) begin
|
next_state =state;
|
next_state =state;
|
next_flit_counter =flit_counter;
|
next_flit_counter =flit_counter;
|
next_sent =sent;
|
next_sent =sent;
|
if(en && ~freez ) begin
|
if(en && ~freez ) begin
|
case(sent)
|
case(sent)
|
1'b1: begin
|
1'b1: begin
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
next_state = state + off_clks;
|
next_state = state + off_clks;
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
next_flit_counter = (flit_counter >= pck_size-1'b1) ? {PCK_SIZw{1'b0}} : flit_counter +1'b1;
|
next_flit_counter = (flit_counter >= pck_size-1'b1) ? {PCK_SIZw{1'b0}} : flit_counter +1'b1;
|
next_inject = (flit_counter=={PCK_SIZw{1'b0}});
|
next_inject = (flit_counter=={PCK_SIZw{1'b0}});
|
if (next_flit_counter >= pck_size-1'b1) begin
|
if (next_flit_counter >= pck_size-1'b1) begin
|
if( next_state >= STATE_INIT ) next_sent =1'b0;
|
if( next_state >= STATE_INIT ) next_sent =1'b0;
|
end
|
end
|
end
|
end
|
1'b0:begin
|
1'b0:begin
|
if( next_state < STATE_INIT ) next_sent = 1'b1;
|
if( next_state < STATE_INIT ) next_sent = 1'b1;
|
next_inject= 1'b0;
|
next_inject= 1'b0;
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
next_state = state - on_clks;
|
next_state = state - on_clks;
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
end
|
end
|
endcase
|
endcase
|
end else begin
|
end else begin
|
next_inject= 1'b0;
|
next_inject= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
|
|
always @ (`pronoc_clk_reset_edge )begin
|
always @ (`pronoc_clk_reset_edge )begin
|
if(`pronoc_reset) begin
|
if(`pronoc_reset) begin
|
state <= STATE_INIT;
|
state <= STATE_INIT;
|
inject <= 1'b0;
|
inject <= 1'b0;
|
sent <= 1'b1;
|
sent <= 1'b1;
|
flit_counter<= 0;
|
flit_counter<= 0;
|
pck_size<=2;
|
pck_size<=2;
|
end else begin
|
end else begin
|
if(input_changed)begin
|
if(input_changed)begin
|
state <= STATE_INIT;
|
state <= STATE_INIT;
|
inject <= 1'b0;
|
inject <= 1'b0;
|
sent <= 1'b1;
|
sent <= 1'b1;
|
flit_counter<= 0;
|
flit_counter<= 0;
|
end
|
end
|
|
|
if(flit_counter=={PCK_SIZw{1'b0}}) pck_size<=pck_size_in;
|
if(flit_counter=={PCK_SIZw{1'b0}}) pck_size<=pck_size_in;
|
state <= next_state;
|
state <= next_state;
|
if(ratio!={CNTw{1'b0}}) inject <= next_inject;
|
if(ratio!={CNTw{1'b0}}) inject <= next_inject;
|
sent <= next_sent;
|
sent <= next_sent;
|
flit_counter<= next_flit_counter;
|
flit_counter<= next_flit_counter;
|
|
|
end
|
end
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
/*************************************
|
/*************************************
|
packet_buffer
|
packet_buffer
|
**************************************/
|
**************************************/
|
|
|
|
|
module packet_gen
|
module packet_gen
|
import pronoc_pkg::*;
|
|
#(
|
#(
|
parameter P = 5,
|
parameter NOC_ID=0,
|
parameter PCK_TYPE = "SINGLE_FLIT",
|
parameter P = 5
|
parameter ROUTE_TYPE = "DETERMINISTIC",
|
|
parameter MAX_PCK_NUM = 10000,
|
|
parameter MAX_SIM_CLKs = 100000,
|
|
parameter TIMSTMP_FIFO_NUM=16,
|
|
parameter MIN_PCK_SIZE=2,
|
|
parameter MAX_PCK_SIZ=100
|
|
)(
|
)(
|
clk_counter,
|
clk_counter,
|
pck_wr,
|
pck_wr,
|
pck_rd,
|
pck_rd,
|
current_r_addr,
|
current_r_addr,
|
current_e_addr,
|
current_e_addr,
|
pck_number,
|
pck_number,
|
dest_e_addr_in,
|
dest_e_addr_in,
|
dest_e_addr_o,
|
dest_e_addr_o,
|
pck_timestamp,
|
pck_timestamp,
|
destport,
|
destport,
|
buffer_full,
|
buffer_full,
|
pck_ready,
|
pck_ready,
|
valid_dst,
|
valid_dst,
|
pck_size_in,
|
pck_size_in,
|
pck_size_o,
|
pck_size_o,
|
clk,
|
clk,
|
reset
|
reset
|
);
|
);
|
|
|
|
|
function integer log2;
|
`NOC_CONF
|
input integer number; begin
|
|
log2=(number <=1) ? 1: 0;
|
|
while(2**log2
|
|
log2=log2+1;
|
|
end
|
|
end
|
|
endfunction // log2
|
|
|
|
localparam
|
localparam
|
PCK_CNTw = log2(MAX_PCK_NUM+1),
|
PCK_CNTw = log2(MAX_PCK_NUM+1),
|
CLK_CNTw = log2(MAX_SIM_CLKs+1),
|
CLK_CNTw = log2(MAX_SIM_CLKs+1);
|
PCK_SIZw = log2(MAX_PCK_SIZ);
|
|
|
|
input reset,clk, pck_wr, pck_rd;
|
input reset,clk, pck_wr, pck_rd;
|
input [RAw-1 :0] current_r_addr;
|
input [RAw-1 :0] current_r_addr;
|
input [EAw-1 : 0] current_e_addr;
|
input [EAw-1 : 0] current_e_addr;
|
input [CLK_CNTw-1 :0] clk_counter;
|
input [CLK_CNTw-1 :0] clk_counter;
|
input [PCK_SIZw-1 :0] pck_size_in;
|
input [PCK_SIZw-1 :0] pck_size_in;
|
input [DAw-1 :0] dest_e_addr_in;
|
input [DAw-1 :0] dest_e_addr_in;
|
output [DAw-1 :0] dest_e_addr_o;
|
output [DAw-1 :0] dest_e_addr_o;
|
input valid_dst;
|
input valid_dst;
|
|
|
output [PCK_CNTw-1 :0] pck_number;
|
output [PCK_CNTw-1 :0] pck_number;
|
output [CLK_CNTw-1 :0] pck_timestamp;
|
output [CLK_CNTw-1 :0] pck_timestamp;
|
output [PCK_SIZw-1 :0] pck_size_o;
|
output [PCK_SIZw-1 :0] pck_size_o;
|
output buffer_full,pck_ready;
|
output buffer_full,pck_ready;
|
|
|
output [DSTPw-1 :0] destport;
|
output [DSTPw-1 :0] destport;
|
reg [PCK_CNTw-1 :0] packet_counter;
|
reg [PCK_CNTw-1 :0] packet_counter;
|
wire buffer_empty;
|
wire buffer_empty;
|
|
|
assign pck_ready = ~buffer_empty & valid_dst;
|
assign pck_ready = ~buffer_empty & valid_dst;
|
|
|
generate if(CAST_TYPE == "UNICAST") begin : uni
|
generate if(CAST_TYPE == "UNICAST") begin : uni
|
conventional_routing #(
|
conventional_routing #(
|
|
.NOC_ID(NOC_ID),
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.RAw(RAw),
|
.RAw(RAw),
|
.EAw(EAw),
|
.EAw(EAw),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.LOCATED_IN_NI(1)
|
.LOCATED_IN_NI(1)
|
)
|
)
|
routing_module
|
routing_module
|
(
|
(
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.current_r_addr(current_r_addr),
|
.current_r_addr(current_r_addr),
|
.dest_e_addr(dest_e_addr_o),
|
.dest_e_addr(dest_e_addr_o),
|
.src_e_addr(current_e_addr),
|
.src_e_addr(current_e_addr),
|
.destport(destport)
|
.destport(destport)
|
);
|
);
|
end endgenerate
|
end endgenerate
|
|
|
wire timestamp_fifo_nearly_full , timestamp_fifo_full;
|
wire timestamp_fifo_nearly_full , timestamp_fifo_full;
|
assign buffer_full = (MIN_PCK_SIZE==1) ? timestamp_fifo_nearly_full : timestamp_fifo_full;
|
assign buffer_full = (MIN_PCK_SIZE==1) ? timestamp_fifo_nearly_full : timestamp_fifo_full;
|
|
|
wire [DAw-1 :0] tmp1;
|
wire [DAw-1 :0] tmp1;
|
wire [PCK_SIZw-1 : 0] tmp2;
|
wire [PCK_SIZw-1 : 0] tmp2;
|
|
|
wire recieve_more_than_0;
|
wire recieve_more_than_0;
|
fwft_fifo_bram #(
|
fwft_fifo_bram #(
|
.DATA_WIDTH(CLK_CNTw+PCK_SIZw+DAw),
|
.DATA_WIDTH(CLK_CNTw+PCK_SIZw+DAw),
|
.MAX_DEPTH(TIMSTMP_FIFO_NUM)
|
.MAX_DEPTH(TIMSTMP_FIFO_NUM)
|
)
|
)
|
timestamp_fifo
|
timestamp_fifo
|
(
|
(
|
.din({dest_e_addr_in,pck_size_in,clk_counter}),
|
.din({dest_e_addr_in,pck_size_in,clk_counter}),
|
.wr_en(pck_wr),
|
.wr_en(pck_wr),
|
.rd_en(pck_rd),
|
.rd_en(pck_rd),
|
.dout({tmp1,tmp2,pck_timestamp}),
|
.dout({tmp1,tmp2,pck_timestamp}),
|
.full(timestamp_fifo_full),
|
.full(timestamp_fifo_full),
|
.nearly_full(timestamp_fifo_nearly_full),
|
.nearly_full(timestamp_fifo_nearly_full),
|
.recieve_more_than_0(recieve_more_than_0),
|
.recieve_more_than_0(recieve_more_than_0),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
//assign dest_e_addr_o = dest_e_addr_in;
|
//assign dest_e_addr_o = dest_e_addr_in;
|
|
|
assign dest_e_addr_o =tmp1;
|
assign dest_e_addr_o =tmp1;
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
assign pck_size_o = (PCK_TYPE == "SINGLE_FLIT" )? 1 : tmp2;
|
assign pck_size_o = (PCK_TYPE == "SINGLE_FLIT" )? 1 : tmp2;
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
assign buffer_empty = ~recieve_more_than_0;
|
assign buffer_empty = ~recieve_more_than_0;
|
|
|
/*
|
/*
|
|
|
bram_based_fifo #(
|
bram_based_fifo #(
|
.Dw(CLK_CNTw),
|
.Dw(CLK_CNTw),
|
.B(TIMSTMP_FIFO_NUM)
|
.B(TIMSTMP_FIFO_NUM)
|
)
|
)
|
timestamp_fifo
|
timestamp_fifo
|
(
|
(
|
.din(clk_counter),
|
.din(clk_counter),
|
.wr_en(pck_wr),
|
.wr_en(pck_wr),
|
.rd_en(pck_rd),
|
.rd_en(pck_rd),
|
.dout(pck_timestamp),
|
.dout(pck_timestamp),
|
.full(timestamp_fifo_full),
|
.full(timestamp_fifo_full),
|
.nearly_full(timestamp_fifo_nearly_full),
|
.nearly_full(timestamp_fifo_nearly_full),
|
.empty(buffer_empty),
|
.empty(buffer_empty),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
*/
|
*/
|
|
|
always @ (`pronoc_clk_reset_edge )begin
|
always @ (`pronoc_clk_reset_edge )begin
|
if(`pronoc_reset) begin
|
if(`pronoc_reset) begin
|
packet_counter <= {PCK_CNTw{1'b0}};
|
packet_counter <= {PCK_CNTw{1'b0}};
|
end else begin
|
end else begin
|
if(pck_rd) begin
|
if(pck_rd) begin
|
packet_counter <= packet_counter+1'b1;
|
packet_counter <= packet_counter+1'b1;
|
|
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
assign pck_number = packet_counter;
|
assign pck_number = packet_counter;
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
/********************
|
/********************
|
|
|
distance_gen
|
distance_gen
|
|
|
********************/
|
********************/
|
|
|
module distance_gen #(
|
module distance_gen #(
|
parameter TOPOLOGY = "MESH",
|
parameter TOPOLOGY = "MESH",
|
parameter T1=4,
|
parameter T1=4,
|
parameter T2=4,
|
parameter T2=4,
|
parameter T3=4,
|
parameter T3=4,
|
parameter EAw=2,
|
parameter EAw=2,
|
parameter DISTw=4
|
parameter DISTw=4
|
|
|
)(
|
)(
|
src_e_addr,
|
src_e_addr,
|
dest_e_addr,
|
dest_e_addr,
|
distance
|
distance
|
);
|
);
|
|
|
input [EAw-1 : 0] src_e_addr;
|
input [EAw-1 : 0] src_e_addr;
|
input [EAw-1 : 0] dest_e_addr;
|
input [EAw-1 : 0] dest_e_addr;
|
output [DISTw-1 : 0] distance;
|
output [DISTw-1 : 0] distance;
|
|
|
generate
|
generate
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE")begin : tori_noc
|
if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE")begin : tori_noc
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
mesh_torus_distance_gen #(
|
mesh_torus_distance_gen #(
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.DISTw(DISTw),
|
.DISTw(DISTw),
|
.EAw(EAw)
|
.EAw(EAw)
|
)
|
)
|
distance_gen
|
distance_gen
|
(
|
(
|
.src_e_addr(src_e_addr),
|
.src_e_addr(src_e_addr),
|
.dest_e_addr(dest_e_addr),
|
.dest_e_addr(dest_e_addr),
|
.distance(distance)
|
.distance(distance)
|
);
|
);
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
end else if (TOPOLOGY == "FMESH") begin :fmesh
|
end else if (TOPOLOGY == "FMESH") begin :fmesh
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
fmesh_distance_gen #(
|
fmesh_distance_gen #(
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.DISTw(DISTw),
|
.DISTw(DISTw),
|
.EAw(EAw)
|
.EAw(EAw)
|
)
|
)
|
distance_gen
|
distance_gen
|
(
|
(
|
.src_e_addr(src_e_addr),
|
.src_e_addr(src_e_addr),
|
.dest_e_addr(dest_e_addr),
|
.dest_e_addr(dest_e_addr),
|
.distance(distance)
|
.distance(distance)
|
);
|
);
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
end else if (TOPOLOGY == "FATTREE" || TOPOLOGY == "TREE") begin : fat
|
end else if (TOPOLOGY == "FATTREE" || TOPOLOGY == "TREE") begin : fat
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
fattree_distance_gen #(
|
fattree_distance_gen #(
|
.K(T1),
|
.K(T1),
|
.L(T2)
|
.L(T2)
|
)
|
)
|
distance_gen
|
distance_gen
|
(
|
(
|
.src_addr_encoded(src_e_addr),
|
.src_addr_encoded(src_e_addr),
|
.dest_addr_encoded(dest_e_addr),
|
.dest_addr_encoded(dest_e_addr),
|
.distance(distance)
|
.distance(distance)
|
);
|
);
|
end else if (TOPOLOGY == "STAR") begin
|
end else if (TOPOLOGY == "STAR") begin
|
|
|
assign distance =1 ;
|
assign distance =1 ;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
|
|
