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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ni/] [ni_master.sv] - Diff between revs 54 and 56

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Rev 54	Rev 56
Line 28...	Line 28...
`** Can support CRC32`	`** Can support CRC32`
`**`	`**`
`**`	`**`
`*******************************************************************/`	`*******************************************************************/`

	`include "pronoc_def.v"

`// synthesis translate_off`
`timescale 1ns / 1ps
`// synthesis translate_on`

`module ni_master`	`module ni_master`
`import pronoc_pkg::*;`

`#(`	`#(`
	`parameter NOC_ID=0,`
`parameter MAX_TRANSACTION_WIDTH=10, // Maximum transaction size will be 2 power of MAX_DMA_TRANSACTION_WIDTH words`	`parameter MAX_TRANSACTION_WIDTH=10, // Maximum transaction size will be 2 power of MAX_DMA_TRANSACTION_WIDTH words`
`parameter MAX_BURST_SIZE =256, // in words`	`parameter MAX_BURST_SIZE =256, // in words`
`parameter CRC_EN= "NO",// "YES","NO" if CRC is enable then the CRC32 of all packet data is calculated and sent via tail flit.`	`parameter CRC_EN= "NO",// "YES","NO" if CRC is enable then the CRC32 of all packet data is calculated and sent via tail flit.`
`parameter HDATA_PRECAPw=0,`	`parameter HDATA_PRECAPw=0,`
`// The header Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially)`	`// The header Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially)`
Line 50...	Line 47...
`//wishbone port parameters`	`//wishbone port parameters`
`parameter Dw = 32,`	`parameter Dw = 32,`
`parameter S_Aw = 7,`	`parameter S_Aw = 7,`
`parameter M_Aw = 32,`	`parameter M_Aw = 32,`
`parameter TAGw = 3,`	`parameter TAGw = 3,`
`parameter SELw = 4,`	`parameter SELw = 4`
`parameter PCK_TYPE = "MULTI_FLIT"`
`)`	`)`
`(`	`(`
`//general`	`//general`
`reset,`	`reset,`
`clk,`	`clk,`
Line 100...	Line 96...
`//interrupt interface`	`//interrupt interface`
`irq`	`irq`

`);`	`);`

	`NOC_CONF



`input reset,clk;`	`input reset,clk;`

Line 174...	Line 170...
`assign flit_in_wr= chan_in.flit_chanel.flit_wr;`	`assign flit_in_wr= chan_in.flit_chanel.flit_wr;`
`assign credit_in = chan_in.flit_chanel.credit;`	`assign credit_in = chan_in.flit_chanel.credit;`

`//old ni.v file`	`//old ni.v file`








`localparam`	`localparam`
`CTRL_FLGw=14,`	`CTRL_FLGw=14,`
`CHw=log2(V),`	`CHw=log2(V),`
`BURST_SIZE_w= log2(MAX_BURST_SIZE+1),`	`BURST_SIZE_w= log2(MAX_BURST_SIZE+1),`
`STATUS1w= 2 * CHw + 4;`	`STATUS1w= 2 * CHw + 4;`
Line 245...	Line 234...
`localparam`	`localparam`
`WORLD_SIZE = Dw/8,`	`WORLD_SIZE = Dw/8,`
`OFFSETw= log2(WORLD_SIZE),`	`OFFSETw= log2(WORLD_SIZE),`
`HDw = Fpay - (2*EAw) - DSTPw - WEIGHTw,`	`HDw = Fpay - (2*EAw) - DSTPw - WEIGHTw,`
`PRE_Dw = (HDATA_PRECAPw>0)? HDATA_PRECAPw : 1,`	`PRE_Dw = (HDATA_PRECAPw>0)? HDATA_PRECAPw : 1,`
`MAX_PCK_SIZE_IN_BYTE = MAX_TRANSACTION_WIDTH + log2(Fpay/8),`	`MAX_PCK_SIZE_IN_BYTE = MAX_TRANSACTION_WIDTH + log2(Fpay/8);`
`BEw = (BYTE_EN)? log2(Fpay/8) : 1;`



`reg [BURST_SIZE_w-1 : 0] burst_size, burst_size_next,burst_counter,burst_counter_next;`	`reg [BURST_SIZE_w-1 : 0] burst_size, burst_size_next,burst_counter,burst_counter_next;`
`wire [V-1 : 0] receive_vc_is_busy, send_vc_is_busy;`	`wire [V-1 : 0] receive_vc_is_busy, send_vc_is_busy;`
Line 481...	Line 469...


`//capture data before saving the actual flit in memory`	`//capture data before saving the actual flit in memory`
`if(HDATA_PRECAPw > 0 ) begin : precap`	`if(HDATA_PRECAPw > 0 ) begin : precap`


`wire [EAw-1 : 0] src_endp_addr;`	`wire [EAw-1 : 0] src_endp_addr;`

`extract_header_flit_info #(`	`extract_header_flit_info #(`
	`.NOC_ID(NOC_ID),`
`.DATA_w(HDATA_PRECAPw)`	`.DATA_w(HDATA_PRECAPw)`
`)`	`)`
`data_extractor`	`data_extractor`
`(`	`(`
`.flit_in(flit_in),`	`.flit_in(flit_in),`
Line 889...	Line 877...
`endgenerate`	`endgenerate`



`conventional_routing #(`	`conventional_routing #(`
	`.NOC_ID(NOC_ID),`
`.TOPOLOGY(TOPOLOGY),`	`.TOPOLOGY(TOPOLOGY),`
`.ROUTE_NAME(ROUTE_NAME),`	`.ROUTE_NAME(ROUTE_NAME),`
`.ROUTE_TYPE(ROUTE_TYPE),`	`.ROUTE_TYPE(ROUTE_TYPE),`
`.T1(T1),`	`.T1(T1),`
`.T2(T2),`	`.T2(T2),`
`.T3(T3),`	`.T3(T3),`
`.RAw(RAw),`	`.RAw(RAw),`
`.EAw(EAw),`	`.EAw(EAw),`
`.DSTPw(DSTPw),`	`.DSTPw(DSTPw),`
`.LOCATED_IN_NI(1)`	`.LOCATED_IN_NI(1)`
`)`	`) route_compute (`
`route_compute`
`(`
`.reset(reset),`	`.reset(reset),`
`.clk(clk),`	`.clk(clk),`
`.current_r_addr(current_r_addr),`	`.current_r_addr(current_r_addr),`
`.src_e_addr(current_e_addr),`	`.src_e_addr(current_e_addr),`
`.dest_e_addr(dest_e_addr),`	`.dest_e_addr(dest_e_addr),`
`.destport(destport)`	`.destport(destport)`
`);`	`);`


`header_flit_generator #(`	`header_flit_generator #(`
	`.NOC_ID(NOC_ID),`
`.DATA_w(HDw)`	`.DATA_w(HDw)`
`)`	`) hdr_flit_gen (`
`hdr_flit_gen`
`(`
`.flit_out(hdr_flit_out),`	`.flit_out(hdr_flit_out),`
`.class_in(pck_class),`	`.class_in(pck_class),`
`.dest_e_addr_in(dest_e_addr),`	`.dest_e_addr_in(dest_e_addr),`
`.src_e_addr_in(current_e_addr),`	`.src_e_addr_in(current_e_addr),`
`.destport_in(destport),`	`.destport_in(destport),`
`.vc_num_in(send_vc_enable),`	`.vc_num_in(send_vc_enable),`
`.weight_in(weight),`	`.weight_in(weight),`
`.be_in(be_in),`	`.be_in(be_in),`
`.data_in(hdr_data )`	`.data_in(hdr_data )`

`);`	`);`

`wire [V-1 : 0] wr_vc_send = (fifo_wr) ? send_vc_enable : {V{1'b0}};`	`wire [V-1 : 0] wr_vc_send = (fifo_wr) ? send_vc_enable : {V{1'b0}};`


Line 986...	Line 971...
`wire [Fw-1 : 0] fifo_dout;`	`wire [Fw-1 : 0] fifo_dout;`

`localparam LBw = log2(LB);`	`localparam LBw = log2(LB);`

`flit_buffer #(`	`flit_buffer #(`
	`.V(V),`
`.B(LB),`	`.B(LB),`
`.SSA_EN("NO")`	`.SSA_EN("NO"),`
	`.Fw(Fw),`
	`.PCK_TYPE(PCK_TYPE),`
	`.CAST_TYPE(CAST_TYPE),`
	`.DEBUG_EN(DEBUG_EN)`
`)`	`)`
`the_ififo`	`the_ififo`
`(`	`(`
`.din(flit_in), // Data in`	`.din(flit_in), // Data in`
`.vc_num_wr(flit_in_vc_num),//write virtual chanel`	`.vc_num_wr(flit_in_vc_num),//write virtual chanel`
Line 1006...	Line 996...
`.multiple_dest(),`	`.multiple_dest(),`
`.sub_rd_ptr_ld()`	`.sub_rd_ptr_ld()`
`);`	`);`

`extract_header_flit_info #(`	`extract_header_flit_info #(`
	`.NOC_ID(NOC_ID),`
`.DATA_w (HDw)`	`.DATA_w (HDw)`
`)`	`)`
`extractor`	`extractor`
`(`	`(`
`.flit_in(fifo_dout),`	`.flit_in(fifo_dout),`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ni/] [ni_master.sv] - Diff between revs 54 and 56