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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [mor1k.v] - Diff between revs 38 and 42

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Rev 38 Rev 42
Line 1... Line 1... 
 
 
`timescale       1ns/1ps
 
 
 
 
 
module mor1k #(
 
module mor1k #(
 
 
 
    parameter OPTION_DCACHE_SNOOP = "ENABLED",// "NONE","ENABLED" 
 
 
    parameter FEATURE_INSTRUCTIONCACHE ="ENABLED",// "NONE","ENABLED" 
 
 
    parameter FEATURE_DATACACHE ="ENABLED",// "NONE","ENABLED" 
 
 
    parameter FEATURE_IMMU ="ENABLED",// "NONE","ENABLED" 
 
 
    parameter FEATURE_DMMU="ENABLED",// "NONE","ENABLED" 
    parameter OPTION_OPERAND_WIDTH=32,
 
    parameter OPTION_OPERAND_WIDTH=32,
 
    parameter IRQ_NUM=32
 
    parameter IRQ_NUM=32
 
 
 
 
 
)(
 
)(
 
 
 
 
 
    clk,
 
    clk,
 
    rst,
 
    rst,
 
    cpu_en,
 
    cpu_en,
 
 
 
 
 
 
 
    //snoop_interface
 
 
 
    snoop_adr_i,
 
 
 
    snoop_en_i,
 
 
 
 
 
 
 
 
 
    // Wishbone interface
 
    // Wishbone interface
 
    iwbm_adr_o,
 
    iwbm_adr_o,
 
    iwbm_stb_o,
 
    iwbm_stb_o,
 
    iwbm_cyc_o,
 
    iwbm_cyc_o,
 
    iwbm_sel_o,
 
    iwbm_sel_o,
Line 43... Line 54... 
 
 
 
 
 
 
 
 
    input                clk;
 
    input                clk;
 
    input                rst;
 
    input                rst;
 
 
 
 
 
 
 
 
 
 
 
    input [31:0]          snoop_adr_i;
 
 
 
    input                 snoop_en_i;
 
 
 
 
 
    // Wishbone interface
 
    // Wishbone interface
 
    output [31:0]         iwbm_adr_o;
 
    output [31:0]         iwbm_adr_o;
 
    output                iwbm_stb_o;
 
    output                iwbm_stb_o;
 
    output                iwbm_cyc_o;
 
    output                iwbm_cyc_o;
 
    output [3:0]          iwbm_sel_o;
 
    output [3:0]          iwbm_sel_o;
Line 86... Line 101... 
    // Stall control from debug interface
 
    // Stall control from debug interface
 
    wire                 du_stall_i=~cpu_en;
 
    wire                 du_stall_i=~cpu_en;
 
   // wire                du_stall_o,
 
   // wire                du_stall_o,
 
 
 
 
 
  wire [31:0] dadr_o,iadr_o;
 
  wire [31:0] dadr_o,iadr_o;
 
 
 
  wire [31:0] snoop_adr_i_byte;
 
   assign iwbm_adr_o= {2'b00,iadr_o[31:2]};
 
   assign iwbm_adr_o= {2'b00,iadr_o[31:2]};
 
   assign dwbm_adr_o= {2'b00,dadr_o[31:2]};
 
   assign dwbm_adr_o= {2'b00,dadr_o[31:2]};
 
 
 
   assign snoop_adr_i_byte= {snoop_adr_i[29:0],2'b00};
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
mor1kx #(
 
mor1kx #(
 
 
 
    .OPTION_DCACHE_SNOOP(OPTION_DCACHE_SNOOP),
 
        .FEATURE_DEBUGUNIT("ENABLED"),
 
        .FEATURE_DEBUGUNIT("ENABLED"),
 
        .FEATURE_CMOV("ENABLED"),
 
        .FEATURE_CMOV("ENABLED"),
 
        .FEATURE_INSTRUCTIONCACHE("ENABLED"),
 
        .FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE),
 
        .OPTION_ICACHE_BLOCK_WIDTH(5),
 
        .OPTION_ICACHE_BLOCK_WIDTH(5),
 
        .OPTION_ICACHE_SET_WIDTH(8),
 
        .OPTION_ICACHE_SET_WIDTH(8),
 
        .OPTION_ICACHE_WAYS(2),
 
        .OPTION_ICACHE_WAYS(2),
 
        .OPTION_ICACHE_LIMIT_WIDTH(32),
 
        .OPTION_ICACHE_LIMIT_WIDTH(32),
 
        .FEATURE_IMMU("ENABLED"),
 
        .FEATURE_IMMU(FEATURE_IMMU),
 
        .FEATURE_DATACACHE("ENABLED"),
 
        .FEATURE_DATACACHE(FEATURE_DATACACHE),
 
        .OPTION_DCACHE_BLOCK_WIDTH(5),
 
        .OPTION_DCACHE_BLOCK_WIDTH(5),
 
        .OPTION_DCACHE_SET_WIDTH(8),
 
        .OPTION_DCACHE_SET_WIDTH(8),
 
        .OPTION_DCACHE_WAYS(2),
 
        .OPTION_DCACHE_WAYS(2),
 
        .OPTION_DCACHE_LIMIT_WIDTH(31),
 
        .OPTION_DCACHE_LIMIT_WIDTH(31),
 
        .FEATURE_DMMU("ENABLED"),
 
        .FEATURE_DMMU(FEATURE_DMMU),
 
        .OPTION_PIC_TRIGGER("LATCHED_LEVEL"),
 
        .OPTION_PIC_TRIGGER("LATCHED_LEVEL"),
 
 
 
 
 
 
 
 
 
        .IBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
 
        .IBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
 
        .DBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
 
        .DBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
 
        .OPTION_CPU0("CAPPUCCINO")
 
        .OPTION_CPU0("CAPPUCCINO")
 
        //.OPTION_RESET_PC(32'hf0000000)
 
        //.OPTION_RESET_PC(32'hf0000000)
 
)
 
)
Line 178... Line 199... 
        .traceport_exec_wben_o   (),
 
        .traceport_exec_wben_o   (),
 
 
 
 
 
        .multicore_coreid_i   (32'd0),
 
        .multicore_coreid_i   (32'd0),
 
        .multicore_numcores_i (32'd0),
 
        .multicore_numcores_i (32'd0),
 
 
 
 
 
        .snoop_adr_i (32'd0),
 
        .snoop_adr_i (snoop_adr_i_byte),
 
        .snoop_en_i  (1'b0),
 
        .snoop_en_i  (snoop_en_i),
 
 
 
 
 
        .du_addr_i(du_addr_i),
 
        .du_addr_i(du_addr_i),
 
    .du_stb_i(du_stb_i),
 
    .du_stb_i(du_stb_i),
 
    .du_dat_i(du_dat_i),
 
    .du_dat_i(du_dat_i),
 
    .du_we_i(du_we_i),
 
    .du_we_i(du_we_i),

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