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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [verilog/] [mor1kx_cache_lru.v] - Diff between revs 38 and 42

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Rev 38 Rev 42
Line 80... Line 80...
//       .update   (updated_history[((NUMWAYS*(NUMWAYS-1))>>1)-1:0])),
//       .update   (updated_history[((NUMWAYS*(NUMWAYS-1))>>1)-1:0])),
//       .access   (access[NUMWAYS-1:0]),
//       .access   (access[NUMWAYS-1:0]),
//       .lru_pre  (lru_pre[NUMWAYS-1:0]),
//       .lru_pre  (lru_pre[NUMWAYS-1:0]),
//       .lru_post (lru_post[NUMWAYS-1:0]));
//       .lru_post (lru_post[NUMWAYS-1:0]));
 
 
 
`timescale       1ns/1ps
 
 
module mor1kx_cache_lru(/*AUTOARG*/
module mor1kx_cache_lru(/*AUTOARG*/
   // Outputs
   // Outputs
   update, lru_pre, lru_post,
   update, lru_pre, lru_post,
   // Inputs
   // Inputs

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