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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY ieee, technology_lib;
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LIBRARY ieee, common_pkg_lib;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE work.tech_fifo_component_pkg.ALL;
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USE work.tech_fifo_component_pkg.ALL;
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USE technology_lib.technology_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
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-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
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LIBRARY ip_stratixiv_fifo_lib;
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--LIBRARY ip_stratixiv_fifo_lib;
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--LIBRARY ip_arria10_fifo_lib;
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--LIBRARY ip_arria10_fifo_lib;
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--LIBRARY ip_arria10_e3sge3_fifo_lib;
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--LIBRARY ip_arria10_e3sge3_fifo_lib;
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--LIBRARY ip_arria10_e1sg_fifo_lib;
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--LIBRARY ip_arria10_e1sg_fifo_lib;
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ENTITY tech_fifo_dc_mixed_widths IS
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ENTITY tech_fifo_dc_mixed_widths IS
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0; --c_tech_select_default;
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g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
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g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
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g_wrdat_w : NATURAL;
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g_wrdat_w : NATURAL;
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g_rddat_w : NATURAL
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g_rddat_w : NATURAL
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);
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);
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PORT (
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PORT (
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rdreq : IN STD_LOGIC;
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rdreq : IN STD_LOGIC;
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wrclk : IN STD_LOGIC;
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wrclk : IN STD_LOGIC;
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wrreq : IN STD_LOGIC;
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wrreq : IN STD_LOGIC;
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q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
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q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
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rdempty : OUT STD_LOGIC;
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rdempty : OUT STD_LOGIC;
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rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
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rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
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wrfull : OUT STD_LOGIC;
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wrfull : OUT STD_LOGIC;
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wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
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wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
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);
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);
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END tech_fifo_dc_mixed_widths;
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END tech_fifo_dc_mixed_widths;
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ARCHITECTURE str OF tech_fifo_dc_mixed_widths IS
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ARCHITECTURE str OF tech_fifo_dc_mixed_widths IS
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BEGIN
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BEGIN
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gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
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gen_ip_stratixiv : IF g_technology=0 GENERATE
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u0 : ip_stratixiv_fifo_dc_mixed_widths
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u0 : ip_stratixiv_fifo_dc_mixed_widths
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GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
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GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
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PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
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PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
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END GENERATE;
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END GENERATE;
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