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[/] [async_sdm_noc/] [branches/] [clos_opt/] [clos_opt/] [syn/] [script/] [source.tcl] - Diff between revs 76 and 78

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Rev 76 Rev 78
Line 18... Line 18...
# the common verilog source files between VC and SDM
# the common verilog source files between VC and SDM
analyze -format verilog   ../../common/src/cell_lib.v
analyze -format verilog   ../../common/src/cell_lib.v
analyze -format verilog   ../../common/src/ctree.v
analyze -format verilog   ../../common/src/ctree.v
analyze -format sverilog  ../../common/src/dcb.v
analyze -format sverilog  ../../common/src/dcb.v
analyze -format sverilog  ../../common/src/dcb_xy.v
analyze -format sverilog  ../../common/src/dcb_xy.v
 
analyze -format sverilog  ../../common/src/cb.v
analyze -format sverilog  ../../common/src/mnma.v
analyze -format sverilog  ../../common/src/mnma.v
analyze -format sverilog  ../../common/src/mrma.v
analyze -format sverilog  ../../common/src/mrma.v
analyze -format verilog   ../../common/src/mutex_arb.v
analyze -format verilog   ../../common/src/mutex_arb.v
analyze -format sverilog  ../../common/src/pipe4.v
analyze -format sverilog  ../../common/src/pipe4.v
analyze -format verilog   ../../common/src/pipen.v
analyze -format verilog   ../../common/src/pipen.v

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