| Line 53... |
Line 53... |
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-- /* AXI Slave interface */
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-- /* AXI Slave interface */
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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-- symbolsPerTransfer:in i_transactor.t_cnt;
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-- outstandingTransactions:in i_transactor.t_cnt;
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lastTransaction:in boolean;
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lastTransaction:in boolean;
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/* Debug ports. */
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/* Debug ports. */
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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| Line 72... |
Line 70... |
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signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
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signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
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signal i_trigger,trigger:boolean;
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signal i_trigger,trigger:boolean;
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/* BFM signalling. */
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/* BFM signalling. */
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-- signal i_readRequest,i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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-- signal i_readResponse,i_writeResponse:i_transactor.t_bfm;
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signal i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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signal i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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signal i_writeResponse:i_transactor.t_bfm;
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signal i_writeResponse:i_transactor.t_bfm;
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begin
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begin
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i_trigger<=writeRequest.trigger xor i_writeRequest.trigger;
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i_trigger<=writeRequest.trigger xor i_writeRequest.trigger;
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| Line 92... |
Line 88... |
when idle=>
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when idle=>
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if i_trigger then axiTxState<=payload; end if;
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if i_trigger then axiTxState<=payload; end if;
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when payload=>
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when payload=>
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if lastTransaction then axiTxState<=endOfTx; end if;
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if lastTransaction then axiTxState<=endOfTx; end if;
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when endOfTx=>
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when endOfTx=>
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axiTxState<=idle;
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if axiMaster_in.tReady then axiTxState<=idle; end if;
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when others=>axiTxState<=idle;
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when others=>axiTxState<=idle;
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end case;
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end case;
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end if;
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end if;
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end process axi_bfmTx_ns;
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end process axi_bfmTx_ns;
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/* output logic for AXI4-Stream Master Tx BFM. */
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/* output logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_op: process(all) is begin
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axi_bfmTx_op: process(all) is begin
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i_writeResponse<=writeResponse;
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i_writeResponse<=writeResponse;
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i_axiMaster_out<=axiMaster_out;
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i_axiMaster_out.tLast<=false;
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i_axiMaster_out.tLast<=false;
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i_writeResponse.trigger<=false;
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i_writeResponse.trigger<=false;
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case next_axiTxState is
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case next_axiTxState is
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when idle=>
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when idle=>
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| Line 131... |
Line 128... |
end case;
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end case;
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end process axi_bfmTx_op;
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end process axi_bfmTx_op;
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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process(aclk) is begin
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process(aclk) is begin
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if falling_edge(aclk) then
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if rising_edge(aclk) or falling_edge(aclk) then
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next_axiTxState<=axiTxState;
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next_axiTxState<=axiTxState;
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i_writeRequest<=writeRequest;
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i_writeRequest<=writeRequest;
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writeResponse<=i_writeResponse;
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writeResponse<=i_writeResponse;
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axiMaster_out<=i_axiMaster_out;
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axiMaster_out<=i_axiMaster_out;
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trigger<=i_trigger;
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trigger<=i_trigger;
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end if;
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end if;
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end process;
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end process;
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/*
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fastPipelines: entity work.ddr(rtl) generic map(busWidth=>8)
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port map(reset=>reset,
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clk=>aclk,
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d=>next_axiTxState,
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q=>axiTxState
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);
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*/
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dbg_axiTxFSM<=axiTxState;
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dbg_axiTxFSM<=axiTxState;
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end architecture rtl;
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end architecture rtl;
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No newline at end of file
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No newline at end of file
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