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Line 47... |
library altera; use altera.stp;
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library altera; use altera.stp;
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entity user is port(
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entity user is port(
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/* Comment-out for simulation. */
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/* Comment-out for simulation. */
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clk,reset:in std_ulogic;
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clk,nReset:in std_ulogic;
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/* AXI Master interface */
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/* AXI Master interface */
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-- axiMaster_in:in t_axi4StreamTransactor_s2m;
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-- axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s
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/* Debug ports. */
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/* Debug ports. */
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selTxn:in unsigned(3 downto 0):=x"0"
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-- selTxn:in unsigned(3 downto 0):=x"5" -- select PRBS by default.
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);
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);
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end entity user;
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end entity user;
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architecture rtl of user is
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architecture rtl of user is
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signal i_reset:std_ulogic:='0';
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signal i_reset:std_ulogic:='0';
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signal porCnt:unsigned(3 downto 0);
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signal porCnt:unsigned(3 downto 0);
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/* Global counters. */
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/* Global counters. */
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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signal symbolsPerTransfer:t_cnt;
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signal outstandingTransactions:t_cnt;
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signal lastTransaction:boolean;
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/* BFM signalling. */
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/* BFM signalling. */
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signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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signal readResponse,writeResponse:t_bfm;
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signal readResponse,writeResponse:t_bfm;
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/* Tester signals. */
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/* Tester signals. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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signal clk,reset:std_ulogic:='0';
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signal clk,nReset:std_ulogic:='0';
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attribute period:time; attribute period of clk:signal is 10 ps;
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attribute period:time; attribute period of clk:signal is 10 ps;
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/* synthesis translate_on */
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/* synthesis translate_on */
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal anlysr_dataIn:std_logic_vector(255 downto 0);
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signal anlysr_dataIn:std_logic_vector(255 downto 0);
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signal anlysr_trigger:std_ulogic;
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signal anlysr_trigger:std_ulogic;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal irq_write:std_ulogic; -- clock gating.
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signal irq_write:std_ulogic; -- clock gating.
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signal selTxn:unsigned(3 downto 0):=4x"0"; -- select PRBS by default.
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begin
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begin
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/* Bus functional models. */
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/* Bus functional models. */
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axiMaster: entity tauhop.axiBfmMaster(rtl)
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axiMaster: entity tauhop.axiBfmMaster(rtl)
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port map(
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port map(
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aclk=>irq_write, n_areset=>not i_reset,
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aclk=>irq_write, n_areset=>not i_reset,
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Line 97... |
readRequest=>readRequest, writeRequest=>writeRequest,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readResponse=>readResponse, writeResponse=>writeResponse,
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readResponse=>readResponse, writeResponse=>writeResponse,
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axiMaster_in=>axiMaster_in,
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axiMaster_in=>axiMaster_in,
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axiMaster_out=>axiMaster_out,
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axiMaster_out=>axiMaster_out,
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symbolsPerTransfer=>symbolsPerTransfer,
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lastTransaction=>lastTransaction,
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outstandingTransactions=>outstandingTransactions,
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dbg_axiTxFSM=>dbg_axiTxFSM
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dbg_axiTxFSM=>dbg_axiTxFSM
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);
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);
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/* Clocks and reset. */
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/* Clocks and reset. */
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/* Power-on Reset circuitry. */
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/* Power-on Reset circuitry. */
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por: process(reset,clk) is begin
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por: process(nReset,clk) is begin
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if reset then i_reset<='1'; porCnt<=(others=>'1');
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if not nReset then i_reset<='1'; porCnt<=(others=>'1');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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i_reset<='0';
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i_reset<='0';
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if porCnt>0 then i_reset<='1'; porCnt<=porCnt-1; end if;
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if porCnt>0 then i_reset<='1'; porCnt<=porCnt-1; end if;
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end if;
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end if;
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end process por;
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end process por;
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/* synthesis translate_off */
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/* synthesis translate_off */
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clk<=not clk after clk'period/2;
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clk<=not clk after clk'period/2;
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process is begin
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process is begin
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reset<='0'; wait for 1 ps;
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nReset<='0'; wait for 1 ps;
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reset<='1'; wait for 500 ps;
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nReset<='1'; wait for 500 ps;
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reset<='0';
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nReset<='0';
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wait;
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wait;
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end process;
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end process;
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/* synthesis translate_on */
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/* synthesis translate_on */
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/* Simulation Tester. */
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/* Simulation Tester. */
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/* Hardware tester. */
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/* Hardware tester. */
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bist: entity work.tester(rtl) port map(
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bist: entity work.tester(cdcrv) port map(
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clk=>clk, reset=>i_reset,
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clk=>clk, reset=>i_reset,
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axiMaster_in=>axiMaster_in,
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axiMaster_in=>axiMaster_in,
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axiMaster_out=>axiMaster_out,
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axiMaster_out=>axiMaster_out,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readResponse=>readResponse, writeResponse=>writeResponse,
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readResponse=>readResponse, writeResponse=>writeResponse,
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irq_write=>irq_write,
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irq_write=>irq_write,
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symbolsPerTransfer=>symbolsPerTransfer,
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lastTransaction=>lastTransaction,
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outstandingTransactions=>outstandingTransactions,
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selTxn=>selTxn
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selTxn=>selTxn
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);
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);
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end architecture rtl;
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end architecture rtl;
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No newline at end of file
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No newline at end of file
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