/*
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/*
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This file is part of the AXI4 Transactor and Bus Functional Model
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This file is part of the AXI4 Transactor and Bus Functional Model
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(axi4_tlm_bfm) project:
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(axi4_tlm_bfm) project:
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http://www.opencores.org/project,axi4_tlm_bfm
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http://www.opencores.org/project,axi4_tlm_bfm
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Description
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Description
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Synthesisable use case for AXI4 on-chip messaging.
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Synthesisable use case for AXI4 on-chip messaging.
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To Do:
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To Do:
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Author(s):
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Author(s):
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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either version 2.1 of the License, or (at your option) any
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later version.
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later version.
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This source is distributed in the hope that it will be
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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details.
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You should have received a copy of the GNU Lesser General
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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from http://www.opencores.org/lgpl.shtml.
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*/
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all, ieee.math_real.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all, ieee.math_real.all;
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library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
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library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
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/* TODO remove once generic packages are supported. */
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/* TODO remove once generic packages are supported. */
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--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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/* synthesis translate_off */
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/* synthesis translate_off */
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library osvvm; use osvvm.RandomPkg.all, osvvm.CoveragePkg.all;
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library osvvm; use osvvm.RandomPkg.all, osvvm.CoveragePkg.all;
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/* synthesis translate_on */
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/* synthesis translate_on */
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--library altera; use altera.stp;
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--library altera; use altera.stp;
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entity tester is port(
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entity tester is port(
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clk,reset:in std_ulogic;
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clk,reset:in std_ulogic;
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/* AXI Master interface */
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/* AXI Master interface */
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axiMaster_in:buffer t_axi4StreamTransactor_s2m;
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axiMaster_in:buffer t_axi4StreamTransactor_s2m;
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axiMaster_out:in t_axi4StreamTransactor_m2s;
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axiMaster_out:in t_axi4StreamTransactor_m2s;
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/* BFM signalling. */
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/* BFM signalling. */
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readRequest,writeRequest:buffer t_bfm;
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readRequest,writeRequest:buffer t_bfm;
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readResponse,writeResponse:in t_bfm;
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readResponse,writeResponse:in t_bfm;
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irq_write:buffer std_ulogic; -- clock gating.
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irq_write:buffer std_ulogic; -- clock gating.
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lastTransaction:out boolean;
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lastTransaction:out boolean;
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/* Debug ports. */
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/* Debug ports. */
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selTxn:in unsigned(3 downto 0)
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selTxn:in unsigned(3 downto 0)
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);
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);
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end entity tester;
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end entity tester;
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architecture rtl of tester is
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architecture rtl of tester is
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signal locked:std_ulogic;
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signal locked:std_ulogic;
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signal porCnt:unsigned(3 downto 0);
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signal porCnt:unsigned(3 downto 0);
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signal trigger:boolean;
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signal trigger:boolean;
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/* Global counters. */
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/* Global counters. */
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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-- signal symbolsPerTransfer:t_cnt;
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-- signal symbolsPerTransfer:t_cnt;
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-- signal outstandingTransactions:t_cnt;
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-- signal outstandingTransactions:t_cnt;
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-- /* BFM signalling. */
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-- /* BFM signalling. */
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-- signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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-- signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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-- signal readResponse,writeResponse:t_bfm;
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-- signal readResponse,writeResponse:t_bfm;
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type txStates is (idle,transmitting);
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type txStates is (idle,transmitting);
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signal txFSM,i_txFSM:txStates;
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signal txFSM,i_txFSM:txStates;
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/* Tester signals. */
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/* Tester signals. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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attribute period:time; attribute period of clk:signal is 10 ps;
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attribute period:time; attribute period of clk:signal is 10 ps;
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/* synthesis translate_on */
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/* synthesis translate_on */
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signal testerClk:std_ulogic;
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signal testerClk:std_ulogic;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal anlysr_dataIn:std_logic_vector(127 downto 0);
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signal anlysr_dataIn:std_logic_vector(127 downto 0);
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signal anlysr_trigger:std_ulogic;
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signal anlysr_trigger:std_ulogic;
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-- signal axiMaster_in:t_axi4StreamTransactor_s2m;
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-- signal axiMaster_in:t_axi4StreamTransactor_s2m;
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-- signal irq_write:std_ulogic; -- clock gating.
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-- signal irq_write:std_ulogic; -- clock gating.
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signal prbs:t_msg;
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signal prbs:t_msg;
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/* Coverage-driven randomisation. */
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/* Coverage-driven randomisation. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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shared variable rv0:covPType;
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shared variable rv0:covPType;
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/* synthesis translate_on */
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/* synthesis translate_on */
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signal rv:integer;
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signal rv:integer;
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signal pctCovered:real;
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signal pctCovered:real;
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signal isCovered,i_isCovered:boolean;
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signal isCovered,i_isCovered:boolean;
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begin
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begin
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/* PLL to generate tester's clock. */
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/* PLL to generate tester's clock. */
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/* f100MHz: entity altera.pll(syn) port map(
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/* f100MHz: entity altera.pll(syn) port map(
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areset=>'0', --not nReset,
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areset=>'0', --not nReset,
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inclk0=>clk,
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inclk0=>clk,
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c0=>testerClk,
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c0=>testerClk,
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locked=>locked
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locked=>locked
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);
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);
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*/
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*/
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/* Interrupt-request generator. */
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/* Interrupt-request generator. */
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trigger<=txFSM/=i_txFSM or writeResponse.trigger;
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trigger<=txFSM/=i_txFSM or writeResponse.trigger;
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-- trigger<=(txFSM/=i_txFSM and txFSM=transmitting) or writeResponse.trigger; -- fixes bug when multiple transactions occur during endOfTx (this should be illegal).
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-- trigger<=(txFSM/=i_txFSM and txFSM=transmitting) or writeResponse.trigger; -- fixes bug when multiple transactions occur during endOfTx (this should be illegal).
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irq_write<=clk when not reset else '0';
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irq_write<=clk when not reset else '0';
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/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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--anlysr_trigger<='1' when writeRequest.trigger else '0';
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--anlysr_trigger<='1' when writeRequest.trigger else '0';
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anlysr_trigger<='1' when reset else '0';
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anlysr_trigger<='1' when reset else '0';
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/* Disable this for synthesis as this is not currently synthesisable.
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/* Disable this for synthesis as this is not currently synthesisable.
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Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
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Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
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*/
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*/
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/* synthesis translate_off */
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/* synthesis translate_off */
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--framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
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--framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
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/* synthesis translate_on */
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/* synthesis translate_on */
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-- anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
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-- anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
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-- anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
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-- anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
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--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
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--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
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anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
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anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
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anlysr_dataIn(18)<='1' when clk else '0';
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anlysr_dataIn(18)<='1' when clk else '0';
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anlysr_dataIn(19)<='1' when reset else '0';
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anlysr_dataIn(19)<='1' when reset else '0';
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anlysr_dataIn(20)<='1' when irq_write else '0';
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anlysr_dataIn(20)<='1' when irq_write else '0';
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anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
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anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
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anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
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anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
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anlysr_dataIn(54 downto 23)<=std_logic_vector(axiMaster_out.tData);
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anlysr_dataIn(54 downto 23)<=std_logic_vector(axiMaster_out.tData);
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anlysr_dataIn(86 downto 55)<=std_logic_vector(prbs);
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anlysr_dataIn(86 downto 55)<=std_logic_vector(prbs);
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--anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
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--anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
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--anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
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--anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
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anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
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anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
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anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
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anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
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anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
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anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
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anlysr_dataIn(99 downto 98)<=to_std_logic_vector(dbg_axiTxFSM);
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anlysr_dataIn(99 downto 98)<=to_std_logic_vector(dbg_axiTxFSM);
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anlysr_dataIn(101 downto 98)<=std_logic_vector(porCnt);
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anlysr_dataIn(101 downto 98)<=std_logic_vector(porCnt);
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-- anlysr_dataIn(102)<='1' when locked else '0';
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-- anlysr_dataIn(102)<='1' when locked else '0';
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-- anlysr_dataIn(102)<=locked;
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-- anlysr_dataIn(102)<=locked;
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anlysr_dataIn(anlysr_dataIn'high downto 102)<=(others=>'0');
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anlysr_dataIn(anlysr_dataIn'high downto 102)<=(others=>'0');
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/* Simulate only if you have compiled Altera's simulation libraries. */
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/* Simulate only if you have compiled Altera's simulation libraries. */
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/* i_bist_logicAnalyser: entity altera.stp(syn) port map(
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/* i_bist_logicAnalyser: entity altera.stp(syn) port map(
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acq_clk=>testerClk,
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acq_clk=>testerClk,
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acq_data_in=>anlysr_dataIn,
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acq_data_in=>anlysr_dataIn,
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acq_trigger_in=>"1",
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acq_trigger_in=>"1",
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trigger_in=>anlysr_trigger
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trigger_in=>anlysr_trigger
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);
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);
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*/
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*/
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/* Stimuli sequencer. TODO move to tester/stimuli.
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/* Stimuli sequencer. TODO move to tester/stimuli.
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This emulates the AXI4-Stream Slave.
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This emulates the AXI4-Stream Slave.
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*/
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*/
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/* Simulation-only stimuli sequencer. */
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/* Simulation-only stimuli sequencer. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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process is begin
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process is begin
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/* Fast read. */
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/* Fast read. */
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report "Performing fast read..." severity note;
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report "Performing fast read..." severity note;
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while not axiMaster_out.tLast loop
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while not axiMaster_out.tLast loop
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/* Wait for tValid to assert. */
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/* Wait for tValid to assert. */
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while not axiMaster_out.tValid loop
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while not axiMaster_out.tValid loop
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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end loop;
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end loop;
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axiMaster_in.tReady<=true;
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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axiMaster_in.tReady<=false;
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report "coverage: " & to_string(pctCovered) severity note;
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report "coverage: " & to_string(pctCovered) severity note;
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end loop;
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end loop;
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report "coverage: " & to_string(pctCovered) severity note;
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report "coverage: " & to_string(pctCovered) severity note;
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report "Completed fast read." severity note;
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report "Completed fast read." severity note;
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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/* Normal read. */
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/* Normal read. */
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report "Performing normal read..." severity note;
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report "Performing normal read..." severity note;
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while not axiMaster_out.tLast loop
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while not axiMaster_out.tLast loop
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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/* Wait for tValid to assert. */
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/* Wait for tValid to assert. */
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while not axiMaster_out.tValid loop
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while not axiMaster_out.tValid loop
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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end loop;
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end loop;
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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axiMaster_in.tReady<=true;
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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axiMaster_in.tReady<=false;
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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report "coverage: " & to_string(pctCovered) severity note;
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report "coverage: " & to_string(pctCovered) severity note;
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end loop;
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end loop;
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report "coverage: " & to_string(pctCovered) severity note;
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report "coverage: " & to_string(pctCovered) severity note;
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report "Completed normal read." severity note;
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report "Completed normal read." severity note;
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for i in 0 to 10 loop
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for i in 0 to 10 loop
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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end loop;
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end loop;
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/* One-shot read. */
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/* One-shot read. */
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report "Performing one-shot read..." severity note;
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report "Performing one-shot read..." severity note;
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axiMaster_in.tReady<=true;
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axiMaster_in.tReady<=true;
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|
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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axiMaster_in.tReady<=false;
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|
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report "coverage: " & to_string(pctCovered) severity note;
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report "coverage: " & to_string(pctCovered) severity note;
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report "Completed one-shot read." severity note;
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report "Completed one-shot read." severity note;
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|
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wait;
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wait;
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end process;
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end process;
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/* synthesis translate_on */
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/* synthesis translate_on */
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|
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/* Synthesisable stimuli sequencer. */
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/* Synthesisable stimuli sequencer. */
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/* process(clk) is begin
|
/* process(clk) is begin
|
if falling_edge(clk) then
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if falling_edge(clk) then
|
axiMaster_in.tReady<=false;
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axiMaster_in.tReady<=false;
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--if axiMaster_out.tValid and not axiMaster_out.tLast then
|
--if axiMaster_out.tValid and not axiMaster_out.tLast then
|
if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
|
if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
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axiMaster_in.tReady<=true;
|
axiMaster_in.tReady<=true;
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end if;
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end if;
|
end if;
|
end if;
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end process;
|
end process;
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*/
|
*/
|
|
|
/* Data transmitter. */
|
/* Data transmitter. */
|
/* Use either PRBS (LFSR) stimuli, or OSVVM randomisation stimuli, not both. */
|
/* Use either PRBS (LFSR) stimuli, or OSVVM randomisation stimuli, not both. */
|
i_prbs: entity tauhop.prbs31(rtl)
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i_prbs: entity tauhop.prbs31(rtl)
|
generic map(
|
generic map(
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isParallelLoad=>true,
|
isParallelLoad=>true,
|
tapVector=>(
|
tapVector=>(
|
/* Example polynomial from Wikipedia:
|
/* Example polynomial from Wikipedia:
|
http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
|
http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
|
*/
|
*/
|
0|3|31=>true, 1|2|30 downto 4=>false
|
0|3|31=>true, 1|2|30 downto 4=>false
|
)
|
)
|
)
|
)
|
port map(
|
port map(
|
/* Comment-out for simulation. */
|
/* Comment-out for simulation. */
|
clk=>irq_write, reset=>reset,
|
clk=>irq_write, reset=>reset,
|
en=>trigger,
|
en=>trigger,
|
seed=>32x"ace1",
|
seed=>32x"ace1",
|
prbs=>prbs
|
prbs=>prbs
|
);
|
);
|
|
|
sequencer_ns: process(all) is
|
sequencer_ns: process(all) is
|
variable last:boolean;
|
variable last:boolean;
|
begin
|
begin
|
txFSM<=i_txFSM;
|
txFSM<=i_txFSM;
|
|
|
if reset then txFSM<=idle;
|
if reset then txFSM<=idle;
|
else
|
else
|
case i_txFSM is
|
case i_txFSM is
|
when idle=>
|
when idle=>
|
if not lastTransaction then txFSM<=transmitting; end if;
|
if not lastTransaction then txFSM<=transmitting; end if;
|
last:=false;
|
last:=false;
|
when transmitting=>
|
when transmitting=>
|
--if axiMaster_out.tLast then
|
--if axiMaster_out.tLast then
|
-- txFSM<=idle;
|
-- txFSM<=idle;
|
--end if;
|
--end if;
|
|
|
/* Fixes multiple transactions when axiTxState=endOfTx. Do not allow
|
/* Fixes multiple transactions when axiTxState=endOfTx. Do not allow
|
txFSM to enter idle until a tReady has been received after the
|
txFSM to enter idle until a tReady has been received after the
|
last transaction.
|
last transaction.
|
*/
|
*/
|
if lastTransaction then last:=true; end if;
|
if lastTransaction then last:=true; end if;
|
if axiMaster_in.tReady and last then txFSM<=idle; end if;
|
if axiMaster_in.tReady and last then txFSM<=idle; end if;
|
when others=> null;
|
when others=> null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process sequencer_ns;
|
end process sequencer_ns;
|
|
|
sequencer_op: process(reset,irq_write) is
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sequencer_op: process(reset,irq_write) is
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/* Local procedures to map BFM signals with the package procedure. */
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/* Local procedures to map BFM signals with the package procedure. */
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procedure read(address:in t_addr) is begin
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procedure read(address:in t_addr) is begin
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read(readRequest,address);
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read(readRequest,address);
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end procedure read;
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end procedure read;
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procedure write(data:in t_msg) is begin
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procedure write(data:in t_msg) is begin
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write(request=>writeRequest, address=>(others=>'-'), data=>data);
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write(request=>writeRequest, address=>(others=>'-'), data=>data);
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end procedure write;
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end procedure write;
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variable isPktError:boolean;
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variable isPktError:boolean;
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begin
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begin
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/* Asynchronous reset. */
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/* Asynchronous reset. */
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if reset then rv<=rv0.randCovPoint; rv0.iCover(rv);
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if reset then rv<=rv0.randCovPoint; rv0.iCover(rv);
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elsif falling_edge(irq_write) then
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elsif falling_edge(irq_write) then
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if reset then
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if reset then
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rv<=rv0.randCovPoint;
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rv<=rv0.randCovPoint;
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rv0.iCover(rv);
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rv0.iCover(rv);
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end if;
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end if;
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case txFSM is
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case txFSM is
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when transmitting=>
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when transmitting=>
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if trigger and not isCovered then
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if trigger and not isCovered then
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/* Pseudorandom stimuli generation using OS-VVM. */
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/* Pseudorandom stimuli generation using OS-VVM. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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rv<=rv0.randCovPoint;
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rv<=rv0.randCovPoint;
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rv0.iCover(rv);
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rv0.iCover(rv);
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write(to_signed(rv, axiMaster_out.tData'length));
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write(to_signed(rv, axiMaster_out.tData'length));
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/* synthesis translate_on */
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/* synthesis translate_on */
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/* Pseudorandom stimuli generation using LFSR. */
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/* Pseudorandom stimuli generation using LFSR. */
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/*
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/*
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case selTxn is
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case selTxn is
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when x"1"=> write(32x"12ab34cd");
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when x"1"=> write(32x"12ab34cd");
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when x"2"=> write(32x"12345678");
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when x"2"=> write(32x"12345678");
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when x"3"=> write(32x"87654321");
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when x"3"=> write(32x"87654321");
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when x"4"=> write(32x"abcd1234");
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when x"4"=> write(32x"abcd1234");
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when others=> write(prbs);
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when others=> write(prbs);
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end case;
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end case;
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*/
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*/
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end if;
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end if;
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when others=>null;
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when others=>null;
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end case;
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end case;
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end if;
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end if;
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end process sequencer_op;
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end process sequencer_op;
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sequencer_regs: process(irq_write) is begin
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if falling_edge(irq_write) then
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i_txFSM<=txFSM;
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end if;
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end process sequencer_regs;
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/* simulation only. */
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/* simulation only. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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coverageMonitor: process is
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coverageMonitor: process is
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procedure initialise is begin
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procedure initialise is begin
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rv0.deallocate; --destroy rv0 and all bins.
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rv0.deallocate; --destroy rv0 and all bins.
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rv0.initSeed(rv0'instance_name);
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rv0.initSeed(rv0'instance_name);
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end procedure initialise;
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end procedure initialise;
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|
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begin
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begin
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/* Fast- and normal-reads. */
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/* Fast- and normal-reads. */
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for i in 0 to 1 loop
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for i in 0 to 1 loop
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initialise;
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initialise;
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rv0.addBins(genBin(integer'low,integer'high,512));
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rv0.addBins(genBin(integer'low,integer'high,512));
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|
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wait until isCovered;
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wait until isCovered;
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-- rv0.writeBin;
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-- rv0.writeBin;
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rv0.setCovZero; -- reset all coverage counts to zero.
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rv0.setCovZero; -- reset all coverage counts to zero.
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end loop;
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end loop;
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|
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/* One-shot read. */
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/* One-shot read. */
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initialise;
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initialise;
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rv0.addBins(genBin(integer'low,integer'high,1));
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rv0.addBins(genBin(integer'low,integer'high,1));
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|
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wait until isCovered;
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wait until isCovered;
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-- rv0.writeBin;
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-- rv0.writeBin;
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rv0.setCovZero;
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rv0.setCovZero;
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|
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wait for 500 ps;
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wait for 500 ps;
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std.env.stop;
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std.env.stop;
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end process coverageMonitor;
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end process coverageMonitor;
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process(irq_write) is begin
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process(irq_write) is begin
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if falling_edge(irq_write) then
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if falling_edge(irq_write) then
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pctCovered<=rv0.getCov;
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pctCovered<=rv0.getCov;
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isCovered<=rv0.isCovered;
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isCovered<=rv0.isCovered;
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i_isCovered<=isCovered;
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i_isCovered<=isCovered;
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end if;
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end if;
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end process;
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end process;
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/* synthesis translate_on */
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/* synthesis translate_on */
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|
|
|
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sequencer_regs: process(irq_write) is begin
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if falling_edge(irq_write) then
|
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i_txFSM<=txFSM;
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end if;
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end process sequencer_regs;
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|
|
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lastTransaction<=true when isCovered else false;
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lastTransaction<=true when isCovered else false;
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|
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checker: process(clk) is begin
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checker: process(clk) is begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if axiMaster_in.tReady then
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if axiMaster_in.tReady then
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assert axiMaster_out.tData/="ZZZZZZZZ"
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assert axiMaster_out.tData/="ZZZZZZZZ"
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report "[Error]: tData must be valid when tReady is asserted at the rising edge of the clock." severity error;
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report "[Error]: tData must be valid when tReady is asserted at the rising edge of the clock." severity error;
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end if;
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end if;
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end if;
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end if;
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end process checker;
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end process checker;
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end architecture rtl;
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end architecture rtl;
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