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URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] [trunk/] [workspace/] [synthesis/] [quartus/] [axi4-tlm.qsf] - Diff between revs 30 and 37

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Rev 30 Rev 37
Line 35... Line 35...
#
#
# -------------------------------------------------------------------------- #
# -------------------------------------------------------------------------- #
 
 
 
 
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C7
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY "user"
set_global_assignment -name TOP_LEVEL_ENTITY "user"
 
#set_global_assignment -name TOP_LEVEL_ENTITY "user"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:27:13  SEPTEMBER 06, 2013"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:27:13  SEPTEMBER 06, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION 12.1
set_global_assignment -name LAST_QUARTUS_VERSION 12.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
Line 49... Line 50...
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
 
 
# NEEK kit:
set_location_assignment PIN_M23 -to reset
#set_location_assignment PIN_M23 -to nReset
set_location_assignment PIN_Y2 -to clk
#set_location_assignment PIN_Y2 -to clk
 
#
 
# BeMicro kit:
#set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user-hw-tlm-paper.vhdl"
set_location_assignment PIN_R7 -to reset
 
set_location_assignment PIN_E1 -to clk
 
 
 
 
 
set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
 
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 
 
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-types.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-types.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tlm.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tlm.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"
Line 74... Line 70...
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/galois-lfsr.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/galois-lfsr.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-interface.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-interface.vhdl"
#set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user-hw-tlm-paper.vhdl"
#set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user-hw-tlm-paper.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user.vhdl"
 
set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
 
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 
 
 
 
 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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