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Line 50... |
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_location_assignment PIN_M23 -to reset
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set_location_assignment PIN_M23 -to nReset
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set_location_assignment PIN_Y2 -to clk
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set_location_assignment PIN_Y2 -to clk
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set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
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#set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user-hw-tlm-paper.vhdl"
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-types.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-types.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pll.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pll.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/stp.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/stp.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/prbs-31.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/prbs-31.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/galois-lfsr.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/galois-lfsr.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-interface.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester-cdcrv.vhdl"
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#set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user-hw-tlm-paper.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user.vhdl"
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set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
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#set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user-hw-tlm-paper.vhdl"
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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