# -------------------------------------------------------------------------- #
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# -------------------------------------------------------------------------- #
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#
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#
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# Copyright (C) 1991-2012 Altera Corporation
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# Copyright (C) 1991-2012 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# applicable agreement for further details.
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#
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#
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# -------------------------------------------------------------------------- #
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# -------------------------------------------------------------------------- #
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#
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#
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# Quartus II 32-bit
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# Quartus II 32-bit
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# Version 12.1 Build 177 11/07/2012 SJ Full Version
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# Version 12.1 Build 177 11/07/2012 SJ Full Version
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# Date created = 23:27:13 September 06, 2013
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# Date created = 23:27:13 September 06, 2013
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#
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#
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# -------------------------------------------------------------------------- #
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# -------------------------------------------------------------------------- #
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#
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#
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# Notes:
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# Notes:
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#
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#
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# 1) The default values for assignments are stored in the file:
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# 1) The default values for assignments are stored in the file:
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# axi4-tlm_assignment_defaults.qdf
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# axi4-tlm_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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# assignment_defaults.qdf
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#
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#
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# 2) Altera recommends that you do not modify this file. This
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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# and any changes you make may be lost or overwritten.
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#
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#
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# -------------------------------------------------------------------------- #
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE115F29C7
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set_global_assignment -name DEVICE EP4CE115F29C7
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set_global_assignment -name TOP_LEVEL_ENTITY "user"
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set_global_assignment -name TOP_LEVEL_ENTITY "user"
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#set_global_assignment -name TOP_LEVEL_ENTITY "user"
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:27:13 SEPTEMBER 06, 2013"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:27:13 SEPTEMBER 06, 2013"
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set_global_assignment -name LAST_QUARTUS_VERSION 12.1
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set_global_assignment -name LAST_QUARTUS_VERSION 12.1
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to reset
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk
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# DE2-115
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set_location_assignment PIN_M23 -to nReset
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set_location_assignment PIN_M23 -to nReset
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set_location_assignment PIN_Y2 -to clk
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set_location_assignment PIN_Y2 -to clk
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set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-types.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tauhop-types.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-fsm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/ddr.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pll.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pll.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/stp.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/stp.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/prbs-31.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/prbs-31.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/galois-lfsr.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/galois-lfsr.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester-cdcrv.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester-cdcrv.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user.vhdl"
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#set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user-hw-tlm-paper.vhdl"
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#set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user-hw-tlm-paper.vhdl"
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