URL https://opencores.org/ocsvn/brsfmnce/brsfmnce/trunk

Subversion Repositories brsfmnce

[/] [brsfmnce/] [trunk/] [Sim/] [tb_BRSFmnCE.v] - Diff between revs 2 and 3

Rev 2	Rev 3
Line 29...	Line 29...
`module tb_BRSFmnCE;`	`module tb_BRSFmnCE;`

`// Inputs`	`// Inputs`
`reg Rst;`	`reg Rst;`
`reg Clk;`	`reg Clk;`

	`reg Clr;`

`reg WE;`	`reg WE;`
`reg RE;`
`reg [7:0] DI;`	`reg [7:0] DI;`

`// Outputs`	`reg RE;`
`wire [7:0] DO;`	`wire [7:0] DO;`
`wire ACK;`	`wire ACK;`

`wire FF;`	`wire FF;`
`wire AF;`	`wire AF;`
`wire HF;`	`wire HF;`
`wire AE;`	`wire AE;`
`wire EF;`	`wire EF;`

`wire [10:0] Cnt;`	`wire [10:0] Cnt;`

`integer i;`	`integer i;`

`// Instantiate the Unit Under Test (UUT)`	`// Instantiate the Unit Under Test (UUT)`

`BRSFmnCE uut (`	`BRSFmnCE uut (`
`.Rst(Rst),`	`.Rst(Rst),`
`.Clk(Clk),`	`.Clk(Clk),`

	`.Clr(Clr),`

`.WE(WE),`	`.WE(WE),`
`.DI(DI),`	`.DI(DI),`

`.RE(RE),`	`.RE(RE),`
`.DO(DO),`	`.DO(DO),`
Line 71...	Line 77...

`initial begin`	`initial begin`
`// Initialize Inputs`	`// Initialize Inputs`
`Rst = 1;`	`Rst = 1;`
`Clk = 1;`	`Clk = 1;`
	`Clr = 0;`
`WE = 0;`	`WE = 0;`
`RE = 0;`	`RE = 0;`
`DI = $random(5);`	`DI = $random(5);`

`i = 0;`	`i = 0;`

`// Wait 100 ns for global reset to finish`	`// Wait 100 ns for global reset to finish`
`#106 Rst = 0;`	`#101 Rst = 0;`

`// Add stimulus here`	`// Add stimulus here`

`while (AF != 1) begin`	`while (AF != 1) begin`
`@(posedge Clk) #1;`	`@(posedge Clk) #1;`