| Line 5... |
Line 5... |
// Synthesizer : QuartusII 10.1 sp1
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// Synthesizer : QuartusII 10.1 sp1
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// Place and Route : QuartusII 10.1 sp1
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// Place and Route : QuartusII 10.1 sp1
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// Targets device : Cyclone III
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// Targets device : Cyclone III
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Organization : www.opencores.org
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// Revision : 2.0
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// Revision : 2.1
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// Date : 2012/03/12
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// Date : 2012/03/15
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// Description : addr mask input from debug host via
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// Description : addr mask input from debug host via
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// Virtual JTAG.
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// Virtual JTAG.
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//**************************************************************
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//**************************************************************
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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| Line 19... |
Line 19... |
mask_out4 ,mask_out5 ,mask_out6 ,mask_out7 ,
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mask_out4 ,mask_out5 ,mask_out6 ,mask_out7 ,
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mask_out8 ,mask_out9 ,mask_out10,mask_out11,
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mask_out8 ,mask_out9 ,mask_out10,mask_out11,
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mask_out12,mask_out13,mask_out14,mask_out15
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mask_out12,mask_out13,mask_out14,mask_out15
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);
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);
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parameter addr_width = 32,
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parameter mask_index = 4, //2**mask_index=mask_num
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mask_index = 4, //2**mask_index=mask_num
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mask_enabl = 4,
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mask_num = 16;
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addr_width = 32;
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output [addr_width-1:0] mask_out0;
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output [mask_enabl+addr_width-1:0] mask_out0;
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output [addr_width-1:0] mask_out1;
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output [mask_enabl+addr_width-1:0] mask_out1;
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output [addr_width-1:0] mask_out2;
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output [mask_enabl+addr_width-1:0] mask_out2;
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output [addr_width-1:0] mask_out3;
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output [mask_enabl+addr_width-1:0] mask_out3;
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output [addr_width-1:0] mask_out4;
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output [mask_enabl+addr_width-1:0] mask_out4;
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output [addr_width-1:0] mask_out5;
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output [mask_enabl+addr_width-1:0] mask_out5;
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output [addr_width-1:0] mask_out6;
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output [mask_enabl+addr_width-1:0] mask_out6;
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output [addr_width-1:0] mask_out7;
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output [mask_enabl+addr_width-1:0] mask_out7;
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output [addr_width-1:0] mask_out8;
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output [mask_enabl+addr_width-1:0] mask_out8;
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output [addr_width-1:0] mask_out9;
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output [mask_enabl+addr_width-1:0] mask_out9;
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output [addr_width-1:0] mask_out10;
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output [mask_enabl+addr_width-1:0] mask_out10;
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output [addr_width-1:0] mask_out11;
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output [mask_enabl+addr_width-1:0] mask_out11;
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output [addr_width-1:0] mask_out12;
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output [mask_enabl+addr_width-1:0] mask_out12;
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output [addr_width-1:0] mask_out13;
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output [mask_enabl+addr_width-1:0] mask_out13;
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output [addr_width-1:0] mask_out14;
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output [mask_enabl+addr_width-1:0] mask_out14;
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output [addr_width-1:0] mask_out15;
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output [mask_enabl+addr_width-1:0] mask_out15;
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reg [addr_width-1:0] mask_out0;
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reg [mask_enabl+addr_width-1:0] mask_out0;
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reg [addr_width-1:0] mask_out1;
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reg [mask_enabl+addr_width-1:0] mask_out1;
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reg [addr_width-1:0] mask_out2;
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reg [mask_enabl+addr_width-1:0] mask_out2;
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reg [addr_width-1:0] mask_out3;
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reg [mask_enabl+addr_width-1:0] mask_out3;
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reg [addr_width-1:0] mask_out4;
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reg [mask_enabl+addr_width-1:0] mask_out4;
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reg [addr_width-1:0] mask_out5;
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reg [mask_enabl+addr_width-1:0] mask_out5;
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reg [addr_width-1:0] mask_out6;
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reg [mask_enabl+addr_width-1:0] mask_out6;
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reg [addr_width-1:0] mask_out7;
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reg [mask_enabl+addr_width-1:0] mask_out7;
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reg [addr_width-1:0] mask_out8;
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reg [mask_enabl+addr_width-1:0] mask_out8;
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reg [addr_width-1:0] mask_out9;
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reg [mask_enabl+addr_width-1:0] mask_out9;
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reg [addr_width-1:0] mask_out10;
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reg [mask_enabl+addr_width-1:0] mask_out10;
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reg [addr_width-1:0] mask_out11;
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reg [mask_enabl+addr_width-1:0] mask_out11;
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reg [addr_width-1:0] mask_out12;
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reg [mask_enabl+addr_width-1:0] mask_out12;
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reg [addr_width-1:0] mask_out13;
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reg [mask_enabl+addr_width-1:0] mask_out13;
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reg [addr_width-1:0] mask_out14;
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reg [mask_enabl+addr_width-1:0] mask_out14;
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reg [addr_width-1:0] mask_out15;
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reg [mask_enabl+addr_width-1:0] mask_out15;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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reg tdo;
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reg tdo;
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reg [mask_index+addr_width-1:0] mask_instr_reg;
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reg [mask_index+mask_enabl+addr_width-1:0] mask_instr_reg;
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reg bypass_reg;
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reg bypass_reg;
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wire [1:0] ir_in;
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wire [1:0] ir_in;
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wire mask_instr = ~ir_in[1] & ir_in[0]; // 1
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wire mask_instr = ~ir_in[1] & ir_in[0]; // 1
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wire [mask_index-1:0] mask_id = mask_instr_reg[(mask_index+addr_width-1):addr_width];
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wire [mask_index-1 :0] mask_id = mask_instr_reg[(mask_index+mask_enabl+addr_width-1):(mask_enabl+addr_width)];
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wire [addr_width-1:0] mask_is = mask_instr_reg[(addr_width-1):0];
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wire [mask_enabl+addr_width-1:0] mask_is = mask_instr_reg[ (mask_enabl+addr_width-1):0];
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always @(posedge tck)
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always @(posedge tck)
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begin
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begin
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if (mask_instr && e1dr)
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if (mask_instr && e1dr)
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case (mask_id)
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case (mask_id)
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| Line 112... |
Line 112... |
/* mask_instr Instruction Handler */
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/* mask_instr Instruction Handler */
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always @ (posedge tck)
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always @ (posedge tck)
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if ( mask_instr && cdr )
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if ( mask_instr && cdr )
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mask_instr_reg <= mask_instr_reg;
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mask_instr_reg <= mask_instr_reg;
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else if ( mask_instr && sdr )
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else if ( mask_instr && sdr )
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mask_instr_reg <= {tdi, mask_instr_reg[mask_index+addr_width-1:1]};
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mask_instr_reg <= {tdi, mask_instr_reg[mask_index+mask_enabl+addr_width-1:1]};
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/* Bypass register */
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/* Bypass register */
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always @ (posedge tck)
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always @ (posedge tck)
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bypass_reg = tdi;
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bypass_reg = tdi;
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