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https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
[/] [bustap-jtag/] [trunk/] [rtl/] [up_monitor.v] - Diff between revs 12 and 13
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| Rev 12 |
Rev 13 |
| Line 126... |
Line 126... |
end
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end
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wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
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wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
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// generate capture wr_in
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// generate capture wr_in
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assign capture_in = {trig_cond_ok_pulse,wr_en_d1,inter_cap_cnt,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
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assign capture_in = {trig_cond_ok_pulse,wr_en_d1,inter_cap_cnt,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
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assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
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assign capture_wr = trig_cond_ok_pulse || (addr_mask_ok && trig_cond_ok);
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// generate pre-trigger wr_in
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// generate pre-trigger wr_in
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assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
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assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
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assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
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assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
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always @(posedge clk)
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always @(posedge clk)
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