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//**************************************************************
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// Module : up_monitor.v
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// Platform : Windows xp sp2
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// Simulator : Modelsim 6.5b
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// Synthesizer : QuartusII 10.1 sp1
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// Place and Route : QuartusII 10.1 sp1
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// Targets device : Cyclone III
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Revision : 2.0
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// Date : 2012/03/12
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// Description : Top level glue logic to group together
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// the JTAG input and output modules.
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//**************************************************************
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`timescale 1ns/1ns
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module up_monitor (
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input clk,
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input wr_en,rd_en,
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input [15:2] addr_in,
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input [31:0] data_in
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);
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module up_monitor (up_clk,up_wbe,up_csn,up_addr,up_data_io);
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reg wr_en_d1,rd_en_d1;
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reg [15:2] addr_in_d1;
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input up_clk,up_wbe,up_csn;
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reg [31:0] data_in_d1;
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input [15:2] up_addr;
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input [31:0] up_data_io;
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reg up_csn_d1, up_csn_d2, up_csn_d3, up_csn_d4;
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wire up_csn_neg_pulse;
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wire [47:0] up_bus_content;
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wire [49:0] trig_condition;
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wire trig_en = trig_condition[49];
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wire trig_set = trig_condition[48];
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wire [15:0] trig_addr = trig_condition[47:32];
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wire [31:0] trig_data = trig_condition[31:0];
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reg trig_condition_ok;
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wire [31:0] addr_mask0,addr_mask1,addr_mask2,addr_mask3,addr_mask4,addr_mask5,addr_mask6,addr_mask7,
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wire [31:0] addr_mask0,addr_mask1,addr_mask2,addr_mask3,addr_mask4,addr_mask5,addr_mask6,addr_mask7,
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addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15;
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addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15;
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reg addr_mask_ok;
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reg addr_mask_ok;
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always @(posedge up_clk)
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wire [49:0] trig_cond;
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wire trig_en = trig_cond[49];
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wire trig_set = trig_cond[48];
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wire [15:0] trig_addr = trig_cond[47:32];
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wire [31:0] trig_data = trig_cond[31:0];
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reg trig_cond_ok;
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wire [47:0] capture_in;
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wire capture_wr;
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// bus input pipeline, allowing back-to-back/continuous bus access
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always @(posedge clk)
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begin
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begin
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up_csn_d1 <= up_csn || up_wbe;
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wr_en_d1 <= wr_en;
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up_csn_d2 <= up_csn_d1;
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rd_en_d1 <= rd_en;
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up_csn_d3 <= up_csn_d2;
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addr_in_d1 <= addr_in;
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up_csn_d4 <= up_csn_d3;
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data_in_d1 <= data_in;
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end
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end
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always @(posedge up_clk)
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// address range based capture enable
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always @(posedge clk)
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begin
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begin
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if (( (up_addr[15:2]<=addr_mask0[31:18] && up_addr[15:2]>=addr_mask0[15:2]) ||
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if (((addr_in[15:2]<=addr_mask0[31:18] && addr_in[15:2]>=addr_mask0[15:2]) ||
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(up_addr[15:2]<=addr_mask1[31:18] && up_addr[15:2]>=addr_mask1[15:2]) ||
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(addr_in[15:2]<=addr_mask1[31:18] && addr_in[15:2]>=addr_mask1[15:2]) ||
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(up_addr[15:2]<=addr_mask2[31:18] && up_addr[15:2]>=addr_mask2[15:2]) ||
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(addr_in[15:2]<=addr_mask2[31:18] && addr_in[15:2]>=addr_mask2[15:2]) ||
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(up_addr[15:2]<=addr_mask3[31:18] && up_addr[15:2]>=addr_mask3[15:2]) ||
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(addr_in[15:2]<=addr_mask3[31:18] && addr_in[15:2]>=addr_mask3[15:2]) ||
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(up_addr[15:2]<=addr_mask4[31:18] && up_addr[15:2]>=addr_mask4[15:2]) ||
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(addr_in[15:2]<=addr_mask4[31:18] && addr_in[15:2]>=addr_mask4[15:2]) ||
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(up_addr[15:2]<=addr_mask5[31:18] && up_addr[15:2]>=addr_mask5[15:2]) ||
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(addr_in[15:2]<=addr_mask5[31:18] && addr_in[15:2]>=addr_mask5[15:2]) ||
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(up_addr[15:2]<=addr_mask6[31:18] && up_addr[15:2]>=addr_mask6[15:2]) ||
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(addr_in[15:2]<=addr_mask6[31:18] && addr_in[15:2]>=addr_mask6[15:2]) ||
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(up_addr[15:2]<=addr_mask7[31:18] && up_addr[15:2]>=addr_mask7[15:2])
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(addr_in[15:2]<=addr_mask7[31:18] && addr_in[15:2]>=addr_mask7[15:2])
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) //inclusive address set
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) //inclusive address range set: addr_mask 0 - 7
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&&
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&&
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( (up_addr[15:2]>addr_mask8 [31:18] || up_addr[15:2]<addr_mask8 [15:2]) &&
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((addr_in[15:2]>addr_mask8 [31:18] || addr_in[15:2]<addr_mask8 [15:2]) &&
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(up_addr[15:2]>addr_mask9 [31:18] || up_addr[15:2]<addr_mask9 [15:2]) &&
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(addr_in[15:2]>addr_mask9 [31:18] || addr_in[15:2]<addr_mask9 [15:2]) &&
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(up_addr[15:2]>addr_mask10[31:18] || up_addr[15:2]<addr_mask10[15:2]) &&
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(addr_in[15:2]>addr_mask10[31:18] || addr_in[15:2]<addr_mask10[15:2]) &&
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(up_addr[15:2]>addr_mask11[31:18] || up_addr[15:2]<addr_mask11[15:2]) &&
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(addr_in[15:2]>addr_mask11[31:18] || addr_in[15:2]<addr_mask11[15:2]) &&
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(up_addr[15:2]>addr_mask12[31:18] || up_addr[15:2]<addr_mask12[15:2]) &&
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(addr_in[15:2]>addr_mask12[31:18] || addr_in[15:2]<addr_mask12[15:2]) &&
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(up_addr[15:2]>addr_mask13[31:18] || up_addr[15:2]<addr_mask13[15:2]) &&
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(addr_in[15:2]>addr_mask13[31:18] || addr_in[15:2]<addr_mask13[15:2]) &&
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(up_addr[15:2]>addr_mask14[31:18] || up_addr[15:2]<addr_mask14[15:2]) &&
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(addr_in[15:2]>addr_mask14[31:18] || addr_in[15:2]<addr_mask14[15:2]) &&
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(up_addr[15:2]>addr_mask15[31:18] || up_addr[15:2]<addr_mask15[15:2])
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(addr_in[15:2]>addr_mask15[31:18] || addr_in[15:2]<addr_mask15[15:2])
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) //exclusive address set
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) //exclusive address range set: addr_mask 8 - 15
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)
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)
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addr_mask_ok <= 1;
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addr_mask_ok <= wr_en;
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else
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else
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addr_mask_ok <= 0;
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addr_mask_ok <= 0;
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end
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end
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always @(posedge up_clk)
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// address-data based capture trigger
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always @(posedge clk)
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begin
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begin
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if (trig_en==0)
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if (trig_en==0) // trigger not enabled, trigger gate forced open
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trig_condition_ok <= 1;
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trig_cond_ok <= 1;
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else if (trig_set==0)
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else if (trig_set==0) // trigger enabled and trigger stopped, trigger gate forced close
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trig_condition_ok <= 0;
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trig_cond_ok <= 0;
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else if (up_csn_d1==0 && up_csn_d2==1)
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else // trigger enabled and trigger started, trigger gate conditional open
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if (trig_addr[15:2]==up_addr[15:2] && trig_data==up_data_io)
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if (trig_addr[15:2]==addr_in[15:2] && trig_data==data_in)
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trig_condition_ok <= 1;
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trig_cond_ok <= wr_en;// trigger gate kept open until trigger stoped
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end
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end
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assign up_csn_neg_pulse = !up_csn_d3 && up_csn_d4 && addr_mask_ok && trig_condition_ok;
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// generate capture wr-in
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assign up_bus_content = {up_addr[15:2],2'b0,up_data_io[31:0]};
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assign capture_in = {addr_in_d1[15:2],2'b0,data_in_d1[31:0]};
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assign capture_wr = wr_en_d1 && addr_mask_ok && trig_cond_ok;
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virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
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.clk(up_clk),
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.wr_en(up_csn_neg_pulse),
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.data_in(up_bus_content)
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);
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defparam
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u_virtual_jtag_adda_fifo.data_width = 48,
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u_virtual_jtag_adda_fifo.fifo_depth = 512,
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u_virtual_jtag_adda_fifo.addr_width = 9,
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u_virtual_jtag_adda_fifo.al_full_val = 511,
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u_virtual_jtag_adda_fifo.al_empt_val = 0;
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// instantiate capture mask, as input
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virtual_jtag_addr_mask u_virtual_jtag_addr_mask (
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virtual_jtag_addr_mask u_virtual_jtag_addr_mask (
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.mask_out0(addr_mask0),
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.mask_out0(addr_mask0),
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.mask_out1(addr_mask1),
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.mask_out1(addr_mask1),
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.mask_out2(addr_mask2),
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.mask_out2(addr_mask2),
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.mask_out3(addr_mask3),
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.mask_out3(addr_mask3),
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defparam
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defparam
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u_virtual_jtag_addr_mask.addr_width = 32,
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u_virtual_jtag_addr_mask.addr_width = 32,
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u_virtual_jtag_addr_mask.mask_index = 4,
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u_virtual_jtag_addr_mask.mask_index = 4,
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u_virtual_jtag_addr_mask.mask_num = 16;
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u_virtual_jtag_addr_mask.mask_num = 16;
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// instantiate capture trigger, as input
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virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
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virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
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.trig_out(trig_condition)
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.trig_out(trig_cond)
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);
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);
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defparam
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defparam
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u_virtual_jtag_adda_trig.trig_width = 50;
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u_virtual_jtag_adda_trig.trig_width = 50;
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// instantiate capture fifo, as output
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virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
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.clk(clk),
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.wr_en(capture_wr),
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.data_in(capture_in)
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);
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defparam
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u_virtual_jtag_adda_fifo.data_width = 48,
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u_virtual_jtag_adda_fifo.fifo_depth = 512,
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u_virtual_jtag_adda_fifo.addr_width = 9,
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u_virtual_jtag_adda_fifo.al_full_val = 511,
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u_virtual_jtag_adda_fifo.al_empt_val = 0;
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endmodule
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endmodule
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