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Line 5... |
// Synthesizer : QuartusII 10.1 sp1
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// Synthesizer : QuartusII 10.1 sp1
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// Place and Route : QuartusII 10.1 sp1
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// Place and Route : QuartusII 10.1 sp1
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// Targets device : Cyclone III
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// Targets device : Cyclone III
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Organization : www.opencores.org
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// Revision : 2.0
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// Revision : 2.1
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// Date : 2012/03/12
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// Date : 2012/03/15
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// Description : Common CPU interface to pipelined access
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// Description : Common CPU interface to pipelined access
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// interface converter.
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// interface converter.
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// @Note: Implementation dependent.
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//**************************************************************
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//**************************************************************
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module up_monitor_wrapper (up_clk,up_wbe,up_csn,up_addr,up_data_io);
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module up_monitor_wrapper (up_clk,up_wbe,up_csn,up_addr,up_data_io);
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// common CPU bus interface
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// common CPU bus interface
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input up_clk;
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input up_clk;
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input up_wbe,up_csn;
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input up_wbe,up_csn; // negative logic
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input [15:2] up_addr;
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input [15:2] up_addr;
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input [31:0] up_data_io;
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input [31:0] up_data_io;
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// prepare for generating wr_en pulse
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// filter out glitches on the line with extra 4 clocks
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reg up_wr_d1, up_wr_d2, up_wr_d3;
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reg up_wbe_d1, up_wbe_d2, up_wbe_d3, up_wbe_d4;
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reg up_csn_d1, up_csn_d2, up_csn_d3, up_csn_d4;
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always @(posedge up_clk) begin
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always @(posedge up_clk) begin
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up_wr_d1 <= !up_wbe & !up_csn;
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up_wbe_d1 <= up_wbe;
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up_wr_d2 <= up_wr_d1;
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up_wbe_d2 <= up_wbe_d1;
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up_wr_d3 <= up_wr_d2;
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up_wbe_d3 <= up_wbe_d2;
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up_wbe_d4 <= up_wbe_d3;
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up_csn_d1 <= up_csn;
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up_csn_d2 <= up_csn_d1;
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up_csn_d3 <= up_csn_d2;
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up_csn_d4 <= up_csn_d3;
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end
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end
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reg wr_en_filtered, wr_en_filtered_d1;
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// prepare for generating rd_en pulse
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always @(posedge up_clk) begin
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reg up_rd_d1, up_rd_d2, up_rd_d3;
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// negative logic changed to positive logic, with filter
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wr_en_filtered <= (!up_wbe_d2 & !up_wbe_d3 & !up_wbe_d4) & (!up_csn_d2 & !up_csn_d3 & !up_csn_d4);
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wr_en_filtered_d1 <= wr_en_filtered;
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end
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reg rd_en_filtered, rd_en_filtered_d1;
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always @(posedge up_clk) begin
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always @(posedge up_clk) begin
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up_rd_d1 <= up_wbe & !up_csn;
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// negative logic changed to positive logic, with filter
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up_rd_d2 <= up_rd_d1;
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rd_en_filtered <= (up_wbe_d2 & up_wbe_d3 & up_wbe_d4) & (!up_csn_d2 & !up_csn_d3 & !up_csn_d4);
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up_rd_d3 <= up_rd_d2;
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rd_en_filtered_d1 <= rd_en_filtered;
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end
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// latch the data at rising edge of up_csn(negative logic)
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reg [15:2] up_addr_latch;
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reg [31:0] up_data_latch;
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always @(posedge up_csn) begin
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up_addr_latch <= up_addr;
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up_data_latch <= up_data_io;
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end
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end
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// map to pipelined access interface
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// map to pipelined access interface
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wire clk = up_clk;
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wire clk = up_clk;
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wire wr_en = up_wr_d2 & !up_wr_d3;
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wire wr_en = !wr_en_filtered & wr_en_filtered_d1; // falling edge of write_enable(positive logic)
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wire rd_en = up_rd_d2 & !up_rd_d3;
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wire rd_en = !rd_en_filtered & rd_en_filtered_d1; // falling edge of read_enable(positive logic)
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wire [15:2] addr_in = up_addr;
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wire [15:2] addr_in = up_addr_latch;
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wire [31:0] data_in = up_data_io;
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wire [31:0] data_in = up_data_latch;
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up_monitor inst (
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up_monitor inst (
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.clk(clk),
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.clk(clk),
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.wr_en(wr_en),
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.wr_en(wr_en),
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.rd_en(rd_en),
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.rd_en(rd_en),
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