| Line 20... |
Line 20... |
* *
|
* *
|
* Xilinx products are not intended for use in life support appliances, *
|
* Xilinx products are not intended for use in life support appliances, *
|
* devices, or systems. Use in such applications are expressly *
|
* devices, or systems. Use in such applications are expressly *
|
* prohibited. *
|
* prohibited. *
|
* *
|
* *
|
* (c) Copyright 1995-2012 Xilinx, Inc. *
|
* (c) Copyright 1995-2014 Xilinx, Inc. *
|
* All rights reserved. *
|
* All rights reserved. *
|
*******************************************************************************/
|
*******************************************************************************/
|
// You must compile the wrapper file scfifo.v when simulating
|
// You must compile the wrapper file scfifo.v when simulating
|
// the core, scfifo. When compiling the wrapper file, be sure to
|
// the core, scfifo. When compiling the wrapper file, be sure to
|
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
| Line 48... |
Line 48... |
data_count
|
data_count
|
);
|
);
|
|
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input [81 : 0] din;
|
input [97 : 0] din;
|
input wr_en;
|
input wr_en;
|
input rd_en;
|
input rd_en;
|
output [81 : 0] dout;
|
output [97 : 0] dout;
|
output full;
|
output full;
|
output empty;
|
output empty;
|
output [9 : 0] data_count;
|
output [9 : 0] data_count;
|
|
|
// synthesis translate_off
|
// synthesis translate_off
|
| Line 86... |
Line 86... |
.C_AXIS_TYPE(0),
|
.C_AXIS_TYPE(0),
|
.C_COMMON_CLOCK(1),
|
.C_COMMON_CLOCK(1),
|
.C_COUNT_TYPE(0),
|
.C_COUNT_TYPE(0),
|
.C_DATA_COUNT_WIDTH(10),
|
.C_DATA_COUNT_WIDTH(10),
|
.C_DEFAULT_VALUE("BlankString"),
|
.C_DEFAULT_VALUE("BlankString"),
|
.C_DIN_WIDTH(82),
|
.C_DIN_WIDTH(98),
|
.C_DIN_WIDTH_AXIS(1),
|
.C_DIN_WIDTH_AXIS(1),
|
.C_DIN_WIDTH_RACH(32),
|
.C_DIN_WIDTH_RACH(32),
|
.C_DIN_WIDTH_RDCH(64),
|
.C_DIN_WIDTH_RDCH(64),
|
.C_DIN_WIDTH_WACH(32),
|
.C_DIN_WIDTH_WACH(32),
|
.C_DIN_WIDTH_WDCH(64),
|
.C_DIN_WIDTH_WDCH(64),
|
.C_DIN_WIDTH_WRCH(2),
|
.C_DIN_WIDTH_WRCH(2),
|
.C_DOUT_RST_VAL("0"),
|
.C_DOUT_RST_VAL("0"),
|
.C_DOUT_WIDTH(82),
|
.C_DOUT_WIDTH(98),
|
.C_ENABLE_RLOCS(0),
|
.C_ENABLE_RLOCS(0),
|
.C_ENABLE_RST_SYNC(1),
|
.C_ENABLE_RST_SYNC(1),
|
.C_ERROR_INJECTION_TYPE(0),
|
.C_ERROR_INJECTION_TYPE(0),
|
.C_ERROR_INJECTION_TYPE_AXIS(0),
|
.C_ERROR_INJECTION_TYPE_AXIS(0),
|
.C_ERROR_INJECTION_TYPE_RACH(0),
|
.C_ERROR_INJECTION_TYPE_RACH(0),
|
