URL https://opencores.org/ocsvn/cpu65c02_true_cycle/cpu65c02_true_cycle/trunk

Subversion Repositories cpu65c02_true_cycle

[/] [cpu65c02_true_cycle/] [trunk/] [TO_DO_list.txt] - Diff between revs 18 and 20

Rev 18	Rev 20
Line 1...	Line 1...
	`(September 09th 2018)`
	`- (WORKING) Performance improvements`
	`- (WORKING) Creating test strategy for RDY signal`
	`- (DONE) Working on reported Bugs/Requests: JMP, Branches, Interrupts, ADC/SBC`
	`- (DONE) Verifying all interrupts`
	`- (90%) Finish working for Specification of cpu65C02_tc`

`(July 31th 2013)`	`(July 31th 2013)`
`- (DONE) Transfer the project state from "BETA" to "RELEASE CANDIDATE"`	`- (DONE) Transfer the project state from "BETA" to "RELEASE CANDIDATE"`
`- (DONE) Offer a high level testbench in assembler for testing all Op Codes`	`- (DONE) Offer a high level testbench in assembler for testing all Op Codes`
`Including Klaus Dormann's "65c02_*_test" suite`	`Including Klaus Dormann's "65c02_*_test" suite`
`- (DONE) Because of translation errors the Verilog sources are no longer`	`- (DONE) Because of translation errors the Verilog sources are no longer`