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[/] [deslcore/] [trunk/] [rtl/] [f_fun.vhd] - Diff between revs 2 and 3

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----------------------------------------------------------------------------------
 
-- Company: 
-- Copyright (c) 2013 Antonio de la Piedra
-- Engineer: 
 
-- 
-- This program is free software: you can redistribute it and/or modify
-- Create Date:    18:16:46 02/19/2013 
-- it under the terms of the GNU General Public License as published by
-- Design Name: 
-- the Free Software Foundation, either version 3 of the License, or
-- Module Name:    f_fun - Behavioral 
-- (at your option) any later version.
-- Project Name: 
 
-- Target Devices: 
-- This program is distributed in the hope that it will be useful,
-- Tool versions: 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- Description: 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--
-- GNU General Public License for more details.
-- Dependencies: 
 
--
-- You should have received a copy of the GNU General Public License
-- Revision: 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
-- Revision 0.01 - File Created
 
-- Additional Comments: 
 
--
 
----------------------------------------------------------------------------------
 
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
 
 
entity f_fun is
entity f_fun is
        port(clk : in std_logic;
        port(clk : in std_logic;
Line 117... Line 114...
                                         r_in(16) & r_in(15)  & r_in(14)  & r_in(13)  & r_in(12)  & r_in(11)  &
                                         r_in(16) & r_in(15)  & r_in(14)  & r_in(13)  & r_in(12)  & r_in(11)  &
                                         r_in(12) & r_in(11)  & r_in(10)  & r_in(9)   & r_in(8)   & r_in(7)   &
                                         r_in(12) & r_in(11)  & r_in(10)  & r_in(9)   & r_in(8)   & r_in(7)   &
                                         r_in(8)  & r_in(7)   & r_in(6)   & r_in(5)   & r_in(4)   & r_in(3)   &
                                         r_in(8)  & r_in(7)   & r_in(6)   & r_in(5)   & r_in(4)   & r_in(3)   &
                                         r_in(4)  & r_in(3)   & r_in(2)   & r_in(1)   & r_in(0)   & r_in(31);
                                         r_in(4)  & r_in(3)   & r_in(2)   & r_in(1)   & r_in(0)   & r_in(31);
 
 
--      DSP_XOR_0 : dsp_xor_48 port map (clk, blk_exp_s, k_in, post_exp_key_add_s);
 
 
 
        post_exp_key_add_s <= blk_exp_s xor k_in;
        post_exp_key_add_s <= blk_exp_s xor k_in;
 
 
        S_BOX_0 : s_box_l_dual_dram port map (post_exp_key_add_s(47 downto 42),
        S_BOX_0 : s_box_l_dual_dram port map (post_exp_key_add_s(47 downto 42),
                                                                                                    (others => '0'),
                                                                                                    (others => '0'),
                                                                                                          post_exp_key_add_s(41 downto 36),
                                                                                                          post_exp_key_add_s(41 downto 36),

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