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// LTX-CREDENCE
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// Project: XXX-X
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//
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// Module: DS1621_b
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// Revision: 01
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// Language: SystemVerilog
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//
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// Engineer: Ashot Khachatryan
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// Function: DS1621 temperature sensor. Behavioral model. Accesses the DS1621_b_nvm.sv memory file. As much RTL as possible.
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//
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// Comments: 20091202 AKH: Created. ADAPTED TO CADENCE IUS8.2
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// 20091216 AKH: Has given up adding the features.
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// DS1621_CNT (8'hA8) & DS1621_SLP (8'hA9) registers are not supported by this model.
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//
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// real board_temp; is defined in the package file for hierarchy independence.
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// It can be declared in this module also but in that case the hierarchy reference to this variable in the test is necessary.
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//
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// The sim environment fragments are present in the accompanying files.
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//
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// I couldn't find the model in the Internet. So, feel free to use it anywhere. This is a gift to everybody, if appropriate...
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//
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`timescale 1ns/10ps
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`ifndef DS1621_STOP
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`define DS1621_STOP 8'h22
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`define DS1621_TH 8'hA1
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`define DS1621_TL 8'hA2
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`define DS1621_CNT 8'hA8
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`define DS1621_SLP 8'hA9
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`define DS1621_TMP 8'hAA
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`define DS1621_CFG 8'hAC
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`define DS1621_STRT 8'hEE
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`endif
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module DS1621_b(
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input SCL
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,inout SDA
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,input A0
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,input A1
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,input A2
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,output TOUT
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);
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parameter tsafe_sim = 1000;
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parameter NVM_WRITE_TM = 10_000_000; // Write time
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parameter NVM_WRITE_CP = 500; // internal clock period
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parameter TMP_CONV_TIM = 1_000_000_000; // Temperature conversion time (can be shortened for simulation in the module instance)
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`define DS1621_ID 4'h9
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real int_tmp;
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shortint TH, TL, TMP;
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reg rst_n, rst_n_d;
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reg POL, ONE_SHOT, t_alarm;
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reg [15:0] TH_init, TL_init, word3_init;
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reg POL_init, ONE_SHOT_init;
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reg [15:0] nv_RAM [2:0];
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reg [15:0] SRi;
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reg [7:0] SRo, SLP, CNT;
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reg [7:0] cur_acc;
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reg [9:0] bit_cnt;
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reg selected, rw_op;
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reg ev_start, ev_stop, ev_TH, ev_TL;
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reg st_write1, st_write2, st_read1, st_read2, st_ack_sl, st_ack_ms, st_pend_memw;
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reg rst_ev_start, rst_sel, bcnt_strt, a_memwr;
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reg int_clk;
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reg [14:0] eewr_tmr; // 'h4E20 = 'd20_000 = 10ms
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reg [20:0] tcnv_tmr; // 'h1E_8480 = 'd2_000_000_000 = 1s
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reg [2:0] iic_sm, iic_smn;
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reg [2:0] eewr_sm, eewr_smn;
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reg [2:0] tcnv_sm, tcnv_smn;
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reg [1:0] byte_cnt, ev_start_r, ev_stop_r;
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reg SDA_r;
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reg a_STOP_r;
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reg THF, TLF; // status bits
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tri1 SDA;
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wire [2:0] A210;
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wire select;
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wire rst_bit_cnt, rst_start, rst_stop, rst_timer, rst_ttimer, rst_byte_cnt, rst_pend, rst_bcnt_strt, rst_a_stop;
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wire THF_reset, TLF_reset, rst_thf, rst_tlf;
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wire [7:0] stat;
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wire DONE, NVB; // status bits
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wire iic_start, ee_start, tcnv_start, timer_done, ttimer_done, a_START_w;
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wire com_idle, com_trfr, com_ackg, wrt_idle, wrt_wait, wrt_done, tcnv_idle, tcnv_wait, tcnv_done;
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wire a_TH, a_TL, a_CNT, a_SLP, a_TMP, a_CFG;
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wire byte_cmd, byte_one, byte_two, byte_thr, two_byte_cmd;
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initial begin int_clk = 0; forever int_clk = #(NVM_WRITE_CP/2) ~int_clk; end // internal clock for EEPROM / Temperature convertion operations
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// access units
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assign a_STOP = SRi[7:0] == `DS1621_STOP;
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assign a_TH = SRi[7:0] == `DS1621_TH;
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assign a_TL = SRi[7:0] == `DS1621_TL;
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assign a_CNT = SRi[7:0] == `DS1621_CNT;
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assign a_SLP = SRi[7:0] == `DS1621_SLP;
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assign a_TMP = SRi[7:0] == `DS1621_TMP;
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assign a_CFG = SRi[7:0] == `DS1621_CFG;
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assign a_STRT = SRi[7:0] == `DS1621_STRT;
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// conditions
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assign A210 = {A2, A1, A0};
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assign select = ev_start & (SRi[7:1] == {`DS1621_ID, A210});
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assign stat = {DONE, THF, TLF, NVB, 2'b00, POL, ONE_SHOT};
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assign rst_bit_cnt = ev_stop | ((bcnt_strt | bit_cnt[9]) & ~SCL) | ~rst_n;
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assign rst_bcnt_strt = ~SCL | ~rst_n;
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assign rst_start = rst_ev_start | ev_stop | ~rst_n;
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assign rst_timer = wrt_done | ~rst_n;
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assign rst_ttimer = tcnv_done | ~rst_n;
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assign rst_byte_cnt = bcnt_strt | ~rst_n; //rst_ev_start
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assign rst_pend = (rst_timer & st_pend_memw) | ~rst_n;
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assign rst_sel = (~ev_start_r[1] & ev_start_r[0]) | ev_stop | ~rst_n;
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assign rst_stop = &ev_stop_r[1:0] | ~rst_n;
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assign rst_a_stop = a_START_w | ~rst_n;
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assign rst_thf = THF_reset | ~rst_n_d;
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assign rst_tlf = TLF_reset | ~rst_n_d;
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assign a_START_w = a_STRT & selected & byte_one & bit_cnt[8] & ~SCL & ~rw_op;
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assign iic_start = (ev_start & ~SCL) | (bit_cnt[0] & selected);
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assign ee_start = st_pend_memw & ev_stop;
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assign tcnv_start = (ONE_SHOT & a_START_w) | (~ONE_SHOT & tcnv_idle & ~a_STOP_r);
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assign timer_done = wrt_wait & (eewr_tmr == (NVM_WRITE_TM / NVM_WRITE_CP));
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assign ttimer_done = tcnv_wait & (tcnv_tmr == (TMP_CONV_TIM / NVM_WRITE_CP));
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assign byte_cmd = byte_cnt == 2'b00;
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assign byte_one = byte_cnt == 2'b01;
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assign byte_two = byte_cnt == 2'b10;
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assign byte_thr = byte_cnt == 2'b11;
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// status bits
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assign NVB = ~wrt_idle;
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assign DONE = tcnv_idle;
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assign THF_reset = ~rw_op & bit_cnt[8] & cur_acc[1] & byte_two & ~SCL & ~SRi[6];
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assign TLF_reset = ~rw_op & bit_cnt[8] & cur_acc[1] & byte_two & ~SCL & ~SRi[5];
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// Start
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always @( negedge SDA, posedge rst_start )
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if ( rst_start ) ev_start <= 1'b0;
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else if ( SCL ) ev_start <= 1'b1;
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always @( negedge SCL ) rst_ev_start <= bit_cnt[9] & ev_start;
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//
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// Stop
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always @( posedge SDA, posedge rst_stop )
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if ( rst_stop ) ev_stop <= 1'b0;
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else if ( SCL ) ev_stop <= 1'b1; // one int_clk period
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always @( posedge int_clk, negedge rst_n )
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if ( ~rst_n ) ev_stop_r[1:0] <= 1'b0;
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else ev_stop_r[1:0] <= {ev_stop_r[0], ev_stop};
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//
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// bit counter
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always @( posedge SCL, posedge rst_bit_cnt )
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if ( rst_bit_cnt ) bit_cnt <= 10'h001;
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else bit_cnt <= {bit_cnt, 1'b0};
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always @( posedge ev_start, posedge rst_bcnt_strt ) // reset after the start condition received
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if ( rst_bcnt_strt ) bcnt_strt <= 1'b0;
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else bcnt_strt <= 1'b1;
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//
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// byte counter
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always @( negedge SCL, posedge rst_byte_cnt )
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if ( rst_byte_cnt ) byte_cnt <= 2'b00;
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else if ( bit_cnt[9] & selected ) byte_cnt <= byte_cnt +1;
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// EEPROM write timer
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always @( posedge int_clk, posedge rst_timer )
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if ( rst_timer ) eewr_tmr <= 15'h0000;
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else if ( wrt_wait ) eewr_tmr <= eewr_tmr +1;
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// Temperature conversion timer
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always @( posedge int_clk, posedge rst_ttimer )
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if ( rst_ttimer ) tcnv_tmr <= 21'h00_0000;
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else if ( tcnv_wait ) tcnv_tmr <= tcnv_tmr +1;
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// Operation control
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always @( negedge SCL, posedge rst_sel )
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if ( rst_sel ) rw_op <= 1'b1;
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else if ( bit_cnt[8] & ev_start & select ) rw_op <= SRi[0]; // wr=0, rd=1
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always @( negedge SCL, posedge rst_sel )
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if ( rst_sel ) selected <= 1'b0;
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else if ( bit_cnt[8] & ev_start & select ) selected <= 1'b1;
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always @( posedge int_clk, negedge rst_n )
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if ( ~rst_n ) ev_start_r[1:0] <= 1'b0;
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else ev_start_r[1:0] <= {ev_start_r[0], ev_start};
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//
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// Current resource being accessed
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always @( negedge SCL, negedge rst_n )
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if ( ~rst_n ) cur_acc[7:0] <= 0;
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else if ( bit_cnt[8] & selected & ~rw_op & byte_one ) cur_acc[7:0] <= {a_STOP, a_TH, a_TL, a_CNT, a_SLP, a_TMP, a_CFG, a_STRT};
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// STOP command retention for not ONE_SHOT mode
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always @( negedge SCL, posedge rst_a_stop )
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if ( rst_a_stop ) a_STOP_r <= 1'b0;
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else if ( cur_acc[7] ) a_STOP_r <= 1'b1;
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// Pending NV memory write flag
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always @( negedge SCL, posedge rst_pend )
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if ( rst_pend ) st_pend_memw <= 0;
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else if ( bit_cnt[9] ) st_pend_memw <= a_memwr | st_pend_memw;
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always @( negedge SCL, posedge rst_pend )
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if ( rst_pend ) a_memwr <= 0;
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else if ( bit_cnt[8] & selected ) a_memwr <= ( ( byte_thr & ((cur_acc[6] & (SRi[15:0] != TH_init)) || (cur_acc[5] & (SRi[15:0] != TL_init))) )
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|| ( byte_two & cur_acc[1] & (SRi[1:0] != word3_init[1:0]) )
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) & ~rw_op & bit_cnt[8];
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//
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// Slave ACK
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always @( negedge SCL, negedge rst_n )
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if ( ~rst_n ) st_ack_sl <= 1'b0;
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else if ( bit_cnt[8] & (~rw_op | ev_start) ) st_ack_sl <= 1'b1;
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else st_ack_sl <= 1'b0;
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// Master ACK
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always @( negedge SCL, negedge rst_n )
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if ( ~rst_n ) st_ack_ms <= 1'b0;
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else if ( bit_cnt[8] & rw_op & ~ev_start ) st_ack_ms <= 1'b1;
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else st_ack_ms <= 1'b0;
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// Shift register: input
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always @( posedge SCL, negedge rst_n )
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if ( ~rst_n ) SRi[15:0] <= 16'h0000;
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else if ( ~st_ack_sl & ~st_ack_ms ) SRi[15:0] <= {SRi[14:0], SDA};
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// Shift register: output
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always @(negedge SCL) // a_STOP, a_TH, a_TL, a_CNT, a_SLP, a_TMP, a_CFG, a_STRT
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if ( bit_cnt[9] ) SRo[7:0] <= cur_acc[6] ? (byte_cmd ? TH[15:8] : TH[7:0]) :
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cur_acc[5] ? (byte_cmd ? TL[15:8] : TL[7:0]) :
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cur_acc[2] ? (byte_cmd ? TMP[15:8] : TMP[7:0]) :
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cur_acc[1] ? stat : 8'hff;
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else SRo[7:0] <= {SRo[6:0], 1'b1};
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// DS1621 registers
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// TH
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always @( negedge SCL, negedge rst_n_d )
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if ( ~rst_n_d ) TH[15:8] <= TH_init[15:8];
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else if ( ~rw_op & bit_cnt[8] & cur_acc[6] & byte_two & ~wrt_wait ) TH[15:8] <= SRi[7:0];
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always @( negedge SCL, negedge rst_n_d )
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if ( ~rst_n_d ) TH[7:0] <= TH_init[7:0];
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else if ( ~rw_op & bit_cnt[8] & cur_acc[6] & byte_thr & ~wrt_wait ) TH[7:0] <= SRi[7:0];
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//
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// TL
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always @( negedge SCL, negedge rst_n_d )
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if ( ~rst_n_d ) TL[15:8] <= TL_init[15:8];
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else if ( ~rw_op & bit_cnt[8] & cur_acc[5] & byte_two & ~wrt_wait ) TL[15:8] <= SRi[7:0];
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always @( negedge SCL, negedge rst_n_d )
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if ( ~rst_n_d ) TL[7:0] <= TL_init[7:0];
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else if ( ~rw_op & bit_cnt[8] & cur_acc[5] & byte_thr & ~wrt_wait ) TL[7:0] <= SRi[7:0];
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//
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// CFG status bits: POL, ONE_SHOT
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always @( negedge SCL, negedge rst_n_d )
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if ( ~rst_n_d ) begin
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POL <= POL_init;
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ONE_SHOT <= ONE_SHOT_init;
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end
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else if ( ~rw_op & bit_cnt[8] & cur_acc[1] & byte_two & ~wrt_wait ) begin
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POL <= SRi[1];
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ONE_SHOT <= SRi[0];
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end
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// THF, TLF
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always @( posedge ev_TH, posedge rst_thf )
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if ( rst_thf ) THF <= 1'b0;
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else THF <= 1'b1;
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// TLF
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always @( posedge ev_TL, posedge rst_tlf )
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if ( rst_tlf ) TLF <= 1'b0;
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else TLF <= 1'b1;
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//
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// Communication state machine
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`define DS1621_IDLE iic_sm[0]
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`define DS1621_TRFR iic_sm[1]
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`define DS1621_ACKG iic_sm[2]
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`define NDS1621_IDLE 3'b001
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`define NDS1621_TRFR 3'b010
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`define NDS1621_ACKG 3'b100
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always @( negedge SCL, negedge rst_n )
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if ( ~rst_n ) iic_sm <= `NDS1621_IDLE;
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else iic_sm <= iic_smn;
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always @( * ) begin
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iic_smn = iic_sm;
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casex( 1 )
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`DS1621_IDLE: if ( iic_start ) iic_smn = `NDS1621_TRFR;
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`DS1621_TRFR: if ( bit_cnt[8] ) iic_smn = `NDS1621_ACKG;
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`DS1621_ACKG: iic_smn = `NDS1621_IDLE;
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default: iic_smn = `NDS1621_IDLE;
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endcase
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end
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assign com_idle = `DS1621_IDLE;
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assign com_trfr = `DS1621_TRFR;
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assign com_ackg = `DS1621_ACKG;
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//
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// EEPROM write state machine
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`define DS1621EE_IDLE eewr_sm[0]
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`define DS1621EE_WAIT eewr_sm[1]
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`define DS1621EE_DONE eewr_sm[2]
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`define NDS1621EE_IDLE 3'b001
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`define NDS1621EE_WAIT 3'b010
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`define NDS1621EE_DONE 3'b100
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always @( posedge int_clk, negedge rst_n )
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if ( ~rst_n ) eewr_sm <= `NDS1621EE_IDLE;
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else eewr_sm <= eewr_smn;
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always @( * ) begin
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eewr_smn = eewr_sm;
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casex( 1 )
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`DS1621EE_IDLE: if ( ee_start ) eewr_smn = `NDS1621EE_WAIT;
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`DS1621EE_WAIT: if ( timer_done ) eewr_smn = `NDS1621EE_DONE;
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`DS1621EE_DONE: eewr_smn = `NDS1621EE_IDLE;
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default: eewr_smn = `NDS1621EE_IDLE;
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endcase
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end
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assign wrt_idle = `DS1621EE_IDLE;
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assign wrt_wait = `DS1621EE_WAIT;
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assign wrt_done = `DS1621EE_DONE;
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//
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// Temperature conversion state machine
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`define DS1621T_IDLE tcnv_sm[0]
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`define DS1621T_WAIT tcnv_sm[1]
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`define DS1621T_DONE tcnv_sm[2]
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`define NDS1621T_IDLE 3'b001
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`define NDS1621T_WAIT 3'b010
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`define NDS1621T_DONE 3'b100
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always @( posedge int_clk, negedge rst_n )
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if ( ~rst_n ) tcnv_sm <= `NDS1621EE_IDLE;
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else tcnv_sm <= tcnv_smn;
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always @( * ) begin
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tcnv_smn = tcnv_sm;
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casex( 1 )
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`DS1621T_IDLE: if ( tcnv_start ) tcnv_smn = `NDS1621T_WAIT;
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`DS1621T_WAIT: if ( ttimer_done ) tcnv_smn = `NDS1621T_DONE;
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`DS1621T_DONE: tcnv_smn = `NDS1621T_IDLE;
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default: tcnv_smn = `NDS1621T_IDLE;
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endcase
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end
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assign tcnv_idle = `DS1621T_IDLE;
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assign tcnv_wait = `DS1621T_WAIT;
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assign tcnv_done = `DS1621T_DONE;
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//
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// Temperature conversion, behavioral
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always @( * )
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if ( board_temp < -55.0 ) int_tmp = -55.0;
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else if ( board_temp > 125.0 ) int_tmp = 125.0;
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else int_tmp = board_temp;
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shortint TMP_tmp;
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always @( posedge tcnv_done, negedge rst_n_d )
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if ( ~rst_n_d ) TMP[15:0] = 16'h1700; // initial valkue is 23*C
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else begin
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TMP_tmp = $rtoi(int_tmp);
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TMP[15:8] = TMP_tmp[7:0];
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//$display("After rtoi TMP_tmp=%0h TMP[15:0]=%0h", TMP_tmp, TMP[15:0]);
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if ( (TMP_tmp - int_tmp) != 0 ) TMP[7:0] = 8'h80;
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else TMP[7:0] = 8'h00;
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//$display("Final TMP[15:0]=%0h", TMP[15:0]);
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end
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//
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// Temperature alarm
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assign ev_TH = TMP > TH;
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assign ev_TL = TMP < TL;
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|
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always @( * )
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if ( ~rst_n_d ) t_alarm = 1'b0;
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else if ( ev_TH ) t_alarm = 1'b1;
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else if ( ev_TL ) t_alarm = 1'b0;
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else t_alarm = t_alarm;
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//
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// Output generation
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assign two_byte_cmd = |cur_acc[6:5] | cur_acc[2];
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assign SDA = st_ack_sl ? 1'b0 : selected & rw_op & ~st_ack_ms & (byte_one | (byte_two & two_byte_cmd)) ? SRo[7] : 1'bz;
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assign TOUT = t_alarm ^~ POL;
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|
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// NV memory read & write
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always @( posedge wrt_done, negedge rst_n ) begin
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if ( ~rst_n ) begin
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$readmemh( "DS1621_b_nvm.sv", nv_RAM );
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if ( nv_RAM[0] == 16'hxxxx ) TH_init = 16'h0000;
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else TH_init = nv_RAM[0];
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if ( nv_RAM[1] == 16'hxxxx ) TL_init = 16'h0000;
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else TL_init = nv_RAM[1];
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if ( nv_RAM[2] == 16'hxxxx ) word3_init = 16'h0000;
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else word3_init = nv_RAM[2];
|
|
POL_init = word3_init[1];
|
|
ONE_SHOT_init = word3_init[0];
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|
end
|
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else if ( wrt_done ) begin
|
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nv_RAM[0] = TH;
|
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nv_RAM[1] = TL;
|
|
nv_RAM[2] = {14'h0000, POL, ONE_SHOT};
|
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$writememh( "DS1621_b_nvm.sv", nv_RAM );
|
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end
|
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//$display("TH=%h, TL=%h, POL=%0h, ONE_SHOT=%0h", TH_init, TL_init, POL_init, ONE_SHOT_init);
|
|
end
|
|
|
|
// timing checks
|
|
initial begin
|
|
rst_n = 0;
|
|
rst_n_d = 1; // memory init signal
|
|
#(tsafe_sim / 2)
|
|
rst_n_d = 0;
|
|
#(tsafe_sim / 2)
|
|
rst_n = 1;
|
|
rst_n_d = 1;
|
|
end
|
|
|
|
specify
|
|
specparam
|
|
`ifdef DS1621_STANDARD
|
|
tBUF = 4700, // Bus free time
|
|
tHD_STA = 4000, // SCL+ hold time: start condition [repeated]
|
|
tLOW = 4700, // SCL- width
|
|
tHIGH = 4000, // SCL+ width
|
|
//tHD_DAT = 0, // SDA to SCL+ hold time
|
|
tSU_STA = 4700, // SCL+ to SDA setup time for repeated start
|
|
tSU_DAT = 250, // SDA to SCL+ setup time
|
|
tSU_STO = 4000; // SCL+ to SDA setup time
|
|
`else
|
|
tBUF = 1300, // Bus free time
|
|
tHD_STA = 600, // SCL+ hold time: start condition [repeated]
|
|
tLOW = 1300, // SCL- width
|
|
tHIGH = 600, // SCL+ width
|
|
//tHD_DAT = 0, // SDA to SCL+ hold time
|
|
tSU_STA = 600, // SCL+ to SDA setup time for repeated start
|
|
tSU_DAT = 100, // SDA to SCL+ setup time
|
|
tSU_STO = 600; // SCL+ to SDA setup time
|
|
`endif
|
|
$width( posedge SDA &&& SCL, tBUF );
|
|
$width( negedge SCL, tLOW );
|
|
$width( posedge SCL, tHIGH );
|
|
$hold ( negedge SDA, negedge SCL &&& rst_n, tHD_STA );
|
|
$setup( posedge SCL, negedge SDA &&& rst_n, tSU_STA );
|
|
$setup( SDA, posedge SCL &&& rst_n, tSU_DAT );
|
|
$setup( posedge SCL, posedge SDA &&& rst_n, tSU_STO );
|
|
endspecify
|
|
|
|
endmodule
|