OpenCores
URL https://opencores.org/ocsvn/ether_arp_1g/ether_arp_1g/trunk

Subversion Repositories ether_arp_1g

[/] [ether_arp_1g/] [trunk/] [testbench/] [tb-arp_responder.vhdl] - Diff between revs 3 and 4

Show entire file | Details | Blame | View Log

Rev 3 Rev 4
Line 1... Line 1...
----------------------------------------------------------------------------------
 
-- Company: Carnegie Mellon University, Pittsburgh PA 
 
-- Engineer: Justin Wagner
 
-- 
 
-- Create Date:    7/Oct/2011
 
-- Design Name: 
 
-- Module Name:    tb_arp_package - testbench 
 
-- Project Name: 
 
-- Target Devices:  n/a
 
-- Tool versions: 
 
--
 
-- Dependencies: arp_package.vhdl (Definitions of various constants)
 
--
 
----------------------------------------------------------------------------------
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use std.textio.all;
use work.arp_package.all;
use work.arp_package.all;
Line 184... Line 170...
        for i in 0 to 3 loop
        for i in 0 to 3 loop
            DATA_RX       <= CMP_A_IPV4_ADDR(i);
            DATA_RX       <= CMP_A_IPV4_ADDR(i);
            wait_tb_clk;
            wait_tb_clk;
        end loop;
        end loop;
 
 
        -- Generate THA
        -- Generate THA (Zero since we don't know it!)
        for i in 0 to 5 loop
        for i in 0 to 5 loop
            DATA_RX       <= MY_MAC((47-i*8) downto (40-i*8));
            DATA_RX       <= (others => '0');
            wait_tb_clk;
            wait_tb_clk;
        end loop;
        end loop;
 
 
        -- Generate TPA
        -- Generate TPA
        for i in 0 to 3 loop
        for i in 0 to 3 loop

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.