-- VHDL Entity work.FPadd_stage4.interface
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-- VHDL Entity work.FPadd_stage4.interface
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- 2003-2004. V1.0
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-- 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY FPadd_stage4 IS
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ENTITY FPadd_stage4 IS
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PORT(
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PORT(
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A_SIGN_stage3 : IN std_logic;
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A_SIGN_stage3 : IN std_logic;
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B_XSIGN_stage3 : IN std_logic;
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B_XSIGN_stage3 : IN std_logic;
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EXP_base : IN std_logic_vector (7 DOWNTO 0);
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EXP_base : IN std_logic_vector (7 DOWNTO 0);
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add_out : IN std_logic_vector (28 DOWNTO 0);
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add_out : IN std_logic_vector (28 DOWNTO 0);
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clk : IN std_logic;
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clk : IN std_logic;
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isINF_tab_stage3 : IN std_logic;
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isINF_tab_stage3 : IN std_logic;
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isNaN_stage3 : IN std_logic;
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isNaN_stage3 : IN std_logic;
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isZ_tab_stage3 : IN std_logic;
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isZ_tab_stage3 : IN std_logic;
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EXP_norm : OUT std_logic_vector (7 DOWNTO 0);
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EXP_norm : OUT std_logic_vector (7 DOWNTO 0);
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OV_stage4 : OUT std_logic;
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OV_stage4 : OUT std_logic;
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SIG_norm : OUT std_logic_vector (27 DOWNTO 0);
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SIG_norm : OUT std_logic_vector (27 DOWNTO 0);
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Z_SIGN_stage4 : OUT std_logic;
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Z_SIGN_stage4 : OUT std_logic;
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isINF_tab_stage4 : OUT std_logic;
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isINF_tab_stage4 : OUT std_logic;
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isNaN_stage4 : OUT std_logic;
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isNaN_stage4 : OUT std_logic;
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isZ_tab_stage4 : OUT std_logic;
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isZ_tab_stage4 : OUT std_logic;
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zero_stage4 : OUT std_logic
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zero_stage4 : OUT std_logic
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);
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);
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-- Declarations
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-- Declarations
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END FPadd_stage4 ;
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END FPadd_stage4 ;
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--
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--
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-- VHDL Architecture work.FPadd_stage4.struct
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-- VHDL Architecture work.FPadd_stage4.struct
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
|
-- using Mentor Graphics FPGA Advantage tools.
|
-- using Mentor Graphics FPGA Advantage tools.
|
--
|
--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- Copyright 2003-2004. V1.0
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-- Copyright 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ARCHITECTURE struct OF FPadd_stage4 IS
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ARCHITECTURE struct OF FPadd_stage4 IS
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-- Architecture declarations
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-- Architecture declarations
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-- Non hierarchical truthtable declarations
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-- Non hierarchical truthtable declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL EXP_norm_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_norm_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_selC : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_selC : std_logic_vector(7 DOWNTO 0);
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SIGNAL OV : std_logic;
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SIGNAL OV : std_logic;
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SIGNAL SIG_norm_int : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_norm_int : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_selC : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_selC : std_logic_vector(27 DOWNTO 0);
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SIGNAL Z_SIGN : std_logic;
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SIGNAL Z_SIGN : std_logic;
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SIGNAL add_out_sign : std_logic;
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SIGNAL add_out_sign : std_logic;
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SIGNAL zero : std_logic;
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SIGNAL zero : std_logic;
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-- Component Declarations
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-- Component Declarations
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COMPONENT FPadd_normalize
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COMPONENT FPadd_normalize
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PORT (
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PORT (
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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SIG_in : IN std_logic_vector (27 DOWNTO 0);
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SIG_in : IN std_logic_vector (27 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0);
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SIG_out : OUT std_logic_vector (27 DOWNTO 0);
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SIG_out : OUT std_logic_vector (27 DOWNTO 0);
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zero : OUT std_logic
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zero : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT FPselComplement
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COMPONENT FPselComplement
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GENERIC (
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GENERIC (
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SIG_width : integer := 28
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SIG_width : integer := 28
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);
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);
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PORT (
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PORT (
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SIG_in : IN std_logic_vector (SIG_width DOWNTO 0);
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SIG_in : IN std_logic_vector (SIG_width DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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-- Optional embedded configurations
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- pragma synthesis_off
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FOR ALL : FPadd_normalize USE ENTITY work.FPadd_normalize;
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FOR ALL : FPadd_normalize USE ENTITY work.FPadd_normalize;
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FOR ALL : FPselComplement USE ENTITY work.FPselComplement;
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FOR ALL : FPselComplement USE ENTITY work.FPselComplement;
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-- pragma synthesis_on
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-- pragma synthesis_on
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BEGIN
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BEGIN
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 2 eb2
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-- HDL Embedded Text Block 2 eb2
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-- reg1 1
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-- reg1 1
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PROCESS(clk)
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PROCESS(clk)
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BEGIN
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF RISING_EDGE(clk) THEN
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Z_SIGN_stage4 <= Z_SIGN;
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Z_SIGN_stage4 <= Z_SIGN;
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OV_stage4 <= OV;
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OV_stage4 <= OV;
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EXP_norm <= EXP_norm_int;
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EXP_norm <= EXP_norm_int;
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SIG_norm <= SIG_norm_int;
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SIG_norm <= SIG_norm_int;
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zero_stage4 <= zero;
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zero_stage4 <= zero;
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isINF_tab_stage4 <= isINF_tab_stage3;
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isINF_tab_stage4 <= isINF_tab_stage3;
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isNaN_stage4 <= isNaN_stage3;
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isNaN_stage4 <= isNaN_stage3;
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isZ_tab_stage4 <= isZ_tab_stage3;
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isZ_tab_stage4 <= isZ_tab_stage3;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- HDL Embedded Text Block 4 eb4
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-- HDL Embedded Text Block 4 eb4
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-- eb4 4
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-- eb4 4
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add_out_sign <= add_out(28);
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add_out_sign <= add_out(28);
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-- HDL Embedded Block 6 SignLogic
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-- HDL Embedded Block 6 SignLogic
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-- Non hierarchical truthtable
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-- Non hierarchical truthtable
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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SignLogic_truth_process: PROCESS(A_SIGN_stage3, B_XSIGN_stage3, add_out_sign)
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SignLogic_truth_process: PROCESS(A_SIGN_stage3, B_XSIGN_stage3, add_out_sign)
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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VARIABLE b1_A_SIGN_stage3B_XSIGN_stage3add_out_sign : std_logic_vector(2 DOWNTO 0);
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VARIABLE b1_A_SIGN_stage3B_XSIGN_stage3add_out_sign : std_logic_vector(2 DOWNTO 0);
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BEGIN
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BEGIN
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-- Block 1
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-- Block 1
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b1_A_SIGN_stage3B_XSIGN_stage3add_out_sign := A_SIGN_stage3 & B_XSIGN_stage3 & add_out_sign;
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b1_A_SIGN_stage3B_XSIGN_stage3add_out_sign := A_SIGN_stage3 & B_XSIGN_stage3 & add_out_sign;
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CASE b1_A_SIGN_stage3B_XSIGN_stage3add_out_sign IS
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CASE b1_A_SIGN_stage3B_XSIGN_stage3add_out_sign IS
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WHEN "000" =>
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WHEN "000" =>
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OV <= '0';
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OV <= '0';
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Z_SIGN <= '0';
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Z_SIGN <= '0';
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WHEN "001" =>
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WHEN "001" =>
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OV <= '1';
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OV <= '1';
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Z_SIGN <= '0';
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Z_SIGN <= '0';
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WHEN "010" =>
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WHEN "010" =>
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OV <= '0';
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OV <= '0';
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Z_SIGN <= '0';
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Z_SIGN <= '0';
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WHEN "011" =>
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WHEN "011" =>
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OV <= '0';
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OV <= '0';
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Z_SIGN <= '1';
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Z_SIGN <= '1';
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WHEN "100" =>
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WHEN "100" =>
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OV <= '0';
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OV <= '0';
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Z_SIGN <= '0';
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Z_SIGN <= '0';
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WHEN "101" =>
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WHEN "101" =>
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OV <= '0';
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OV <= '0';
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Z_SIGN <= '1';
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Z_SIGN <= '1';
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WHEN "110" =>
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WHEN "110" =>
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OV <= '0';
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OV <= '0';
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Z_SIGN <= '1';
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Z_SIGN <= '1';
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WHEN "111" =>
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WHEN "111" =>
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OV <= '1';
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OV <= '1';
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Z_SIGN <= '1';
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Z_SIGN <= '1';
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WHEN OTHERS =>
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WHEN OTHERS =>
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OV <= '0';
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OV <= '0';
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Z_SIGN <= '0';
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Z_SIGN <= '0';
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END CASE;
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END CASE;
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END PROCESS SignLogic_truth_process;
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END PROCESS SignLogic_truth_process;
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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-- Instance port mappings.
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-- Instance port mappings.
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I8 : FPadd_normalize
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I8 : FPadd_normalize
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PORT MAP (
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PORT MAP (
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EXP_in => EXP_selC,
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EXP_in => EXP_selC,
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SIG_in => SIG_selC,
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SIG_in => SIG_selC,
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EXP_out => EXP_norm_int,
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EXP_out => EXP_norm_int,
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SIG_out => SIG_norm_int,
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SIG_out => SIG_norm_int,
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zero => zero
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zero => zero
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);
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);
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I12 : FPselComplement
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I12 : FPselComplement
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GENERIC MAP (
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GENERIC MAP (
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SIG_width => 28
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SIG_width => 28
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)
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)
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PORT MAP (
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PORT MAP (
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SIG_in => add_out,
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SIG_in => add_out,
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EXP_in => EXP_base,
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EXP_in => EXP_base,
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SIG_out => SIG_selC,
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SIG_out => SIG_selC,
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EXP_out => EXP_selC
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EXP_out => EXP_selC
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);
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);
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END struct;
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END struct;
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