-- VHDL Entity work.FPadd_stage6.interface
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-- VHDL Entity work.FPadd_stage6.interface
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- 2003-2004. V1.0
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-- 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY FPadd_stage6 IS
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ENTITY FPadd_stage6 IS
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PORT(
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PORT(
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OV : IN std_logic;
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OV : IN std_logic;
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SIG_norm2 : IN std_logic_vector (27 DOWNTO 0);
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SIG_norm2 : IN std_logic_vector (27 DOWNTO 0);
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Z_EXP : IN std_logic_vector (7 DOWNTO 0);
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Z_EXP : IN std_logic_vector (7 DOWNTO 0);
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Z_SIGN : IN std_logic;
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Z_SIGN : IN std_logic;
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clk : IN std_logic;
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clk : IN std_logic;
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isINF_tab : IN std_logic;
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isINF_tab : IN std_logic;
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isNaN : IN std_logic;
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isNaN : IN std_logic;
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isZ_tab : IN std_logic;
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isZ_tab : IN std_logic;
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zero : IN std_logic;
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zero : IN std_logic;
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FP_Z : OUT std_logic_vector (31 DOWNTO 0)
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FP_Z : OUT std_logic_vector (31 DOWNTO 0)
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);
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);
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-- Declarations
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-- Declarations
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END FPadd_stage6 ;
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END FPadd_stage6 ;
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--
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--
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-- VHDL Architecture work.FPadd_stage6.struct
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-- VHDL Architecture work.FPadd_stage6.struct
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
|
-- Guillermo Marcus, gmarcus@ieee.org
|
-- using Mentor Graphics FPGA Advantage tools.
|
-- using Mentor Graphics FPGA Advantage tools.
|
--
|
--
|
-- Visit "http://fpga.mty.itesm.mx" for more info.
|
-- Visit "http://fpga.mty.itesm.mx" for more info.
|
--
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--
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-- Copyright 2003-2004. V1.0
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-- Copyright 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ARCHITECTURE struct OF FPadd_stage6 IS
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ARCHITECTURE struct OF FPadd_stage6 IS
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL EXP_isINF : std_logic;
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SIGNAL EXP_isINF : std_logic;
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SIGNAL FP_Z_int : std_logic_vector(31 DOWNTO 0);
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SIGNAL FP_Z_int : std_logic_vector(31 DOWNTO 0);
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SIGNAL Z_SIG : std_logic_vector(22 DOWNTO 0);
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SIGNAL Z_SIG : std_logic_vector(22 DOWNTO 0);
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SIGNAL isINF : std_logic;
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SIGNAL isINF : std_logic;
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SIGNAL isZ : std_logic;
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SIGNAL isZ : std_logic;
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-- Component Declarations
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-- Component Declarations
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COMPONENT PackFP
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COMPONENT PackFP
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PORT (
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PORT (
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SIGN : IN std_logic ;
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SIGN : IN std_logic ;
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EXP : IN std_logic_vector (7 DOWNTO 0);
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EXP : IN std_logic_vector (7 DOWNTO 0);
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SIG : IN std_logic_vector (22 DOWNTO 0);
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SIG : IN std_logic_vector (22 DOWNTO 0);
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isNaN : IN std_logic ;
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isNaN : IN std_logic ;
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isINF : IN std_logic ;
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isINF : IN std_logic ;
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isZ : IN std_logic ;
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isZ : IN std_logic ;
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FP : OUT std_logic_vector (31 DOWNTO 0)
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FP : OUT std_logic_vector (31 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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-- Optional embedded configurations
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- pragma synthesis_off
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FOR ALL : PackFP USE ENTITY work.PackFP;
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FOR ALL : PackFP USE ENTITY work.PackFP;
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-- pragma synthesis_on
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-- pragma synthesis_on
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BEGIN
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BEGIN
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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-- HDL Embedded Text Block 1 eb1
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--reg1 1
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--reg1 1
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PROCESS(clk)
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PROCESS(clk)
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BEGIN
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF RISING_EDGE(clk) THEN
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FP_Z <= FP_Z_int;
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FP_Z <= FP_Z_int;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- HDL Embedded Text Block 2 eb2
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-- HDL Embedded Text Block 2 eb2
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-- eb2 2
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-- eb2 2
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Z_SIG <= SIG_norm2(25 DOWNTO 3);
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Z_SIG <= SIG_norm2(25 DOWNTO 3);
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-- HDL Embedded Text Block 9 eb7
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-- HDL Embedded Text Block 9 eb7
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-- eb7 9
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-- eb7 9
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EXP_isINF <= '1' WHEN (OV='1' OR Z_EXP=X"FF") ELSE '0';
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EXP_isINF <= '1' WHEN (OV='1' OR Z_EXP=X"FF") ELSE '0';
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-- ModuleWare code(v1.1) for instance 'I7' of 'or'
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-- ModuleWare code(v1.1) for instance 'I7' of 'or'
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isINF <= EXP_isINF OR isINF_tab;
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isINF <= EXP_isINF OR isINF_tab;
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-- ModuleWare code(v1.1) for instance 'I17' of 'or'
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-- ModuleWare code(v1.1) for instance 'I17' of 'or'
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isZ <= zero OR isZ_tab;
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isZ <= zero OR isZ_tab;
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-- Instance port mappings.
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-- Instance port mappings.
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I2 : PackFP
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I2 : PackFP
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PORT MAP (
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PORT MAP (
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SIGN => Z_SIGN,
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SIGN => Z_SIGN,
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EXP => Z_EXP,
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EXP => Z_EXP,
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SIG => Z_SIG,
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SIG => Z_SIG,
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isNaN => isNaN,
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isNaN => isNaN,
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isINF => isINF,
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isINF => isINF,
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isZ => isZ,
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isZ => isZ,
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FP => FP_Z_int
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FP => FP_Z_int
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);
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);
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END struct;
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END struct;
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