-- VHDL Entity HAVOC.FPmul_stage1.interface
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-- VHDL Entity HAVOC.FPmul_stage1.interface
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- 2003-2004. V1.0
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-- 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY FPmul_stage1 IS
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ENTITY FPmul_stage1 IS
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PORT(
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PORT(
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FP_A : IN std_logic_vector (31 DOWNTO 0);
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FP_A : IN std_logic_vector (31 DOWNTO 0);
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FP_B : IN std_logic_vector (31 DOWNTO 0);
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FP_B : IN std_logic_vector (31 DOWNTO 0);
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clk : IN std_logic;
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clk : IN std_logic;
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A_EXP : OUT std_logic_vector (7 DOWNTO 0);
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A_EXP : OUT std_logic_vector (7 DOWNTO 0);
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A_SIG : OUT std_logic_vector (31 DOWNTO 0);
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A_SIG : OUT std_logic_vector (31 DOWNTO 0);
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B_EXP : OUT std_logic_vector (7 DOWNTO 0);
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B_EXP : OUT std_logic_vector (7 DOWNTO 0);
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B_SIG : OUT std_logic_vector (31 DOWNTO 0);
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B_SIG : OUT std_logic_vector (31 DOWNTO 0);
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SIGN_out_stage1 : OUT std_logic;
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SIGN_out_stage1 : OUT std_logic;
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isINF_stage1 : OUT std_logic;
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isINF_stage1 : OUT std_logic;
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isNaN_stage1 : OUT std_logic;
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isNaN_stage1 : OUT std_logic;
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isZ_tab_stage1 : OUT std_logic
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isZ_tab_stage1 : OUT std_logic
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);
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);
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-- Declarations
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-- Declarations
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END FPmul_stage1 ;
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END FPmul_stage1 ;
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--
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--
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-- VHDL Architecture HAVOC.FPmul_stage1.struct
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-- VHDL Architecture HAVOC.FPmul_stage1.struct
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- Copyright 2003-2004. V1.0
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-- Copyright 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ARCHITECTURE struct OF FPmul_stage1 IS
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ARCHITECTURE struct OF FPmul_stage1 IS
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-- Architecture declarations
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-- Architecture declarations
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-- Non hierarchical truthtable declarations
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-- Non hierarchical truthtable declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL A_EXP_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL A_EXP_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL A_SIGN : std_logic;
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SIGNAL A_SIGN : std_logic;
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SIGNAL A_SIG_int : std_logic_vector(31 DOWNTO 0);
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SIGNAL A_SIG_int : std_logic_vector(31 DOWNTO 0);
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SIGNAL A_isINF : std_logic;
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SIGNAL A_isINF : std_logic;
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SIGNAL A_isNaN : std_logic;
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SIGNAL A_isNaN : std_logic;
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SIGNAL A_isZ : std_logic;
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SIGNAL A_isZ : std_logic;
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SIGNAL B_EXP_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL B_EXP_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL B_SIGN : std_logic;
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SIGNAL B_SIGN : std_logic;
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SIGNAL B_SIG_int : std_logic_vector(31 DOWNTO 0);
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SIGNAL B_SIG_int : std_logic_vector(31 DOWNTO 0);
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SIGNAL B_isINF : std_logic;
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SIGNAL B_isINF : std_logic;
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SIGNAL B_isNaN : std_logic;
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SIGNAL B_isNaN : std_logic;
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SIGNAL B_isZ : std_logic;
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SIGNAL B_isZ : std_logic;
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SIGNAL SIGN_out_int : std_logic;
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SIGNAL SIGN_out_int : std_logic;
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SIGNAL isINF_int : std_logic;
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SIGNAL isINF_int : std_logic;
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SIGNAL isNaN_int : std_logic;
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SIGNAL isNaN_int : std_logic;
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SIGNAL isZ_tab_int : std_logic;
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SIGNAL isZ_tab_int : std_logic;
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-- Component Declarations
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-- Component Declarations
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COMPONENT UnpackFP
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COMPONENT UnpackFP
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PORT (
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PORT (
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FP : IN std_logic_vector (31 DOWNTO 0);
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FP : IN std_logic_vector (31 DOWNTO 0);
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SIG : OUT std_logic_vector (31 DOWNTO 0);
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SIG : OUT std_logic_vector (31 DOWNTO 0);
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EXP : OUT std_logic_vector (7 DOWNTO 0);
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EXP : OUT std_logic_vector (7 DOWNTO 0);
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SIGN : OUT std_logic ;
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SIGN : OUT std_logic ;
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isNaN : OUT std_logic ;
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isNaN : OUT std_logic ;
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isINF : OUT std_logic ;
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isINF : OUT std_logic ;
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isZ : OUT std_logic ;
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isZ : OUT std_logic ;
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isDN : OUT std_logic
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isDN : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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-- Optional embedded configurations
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- pragma synthesis_off
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FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
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FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
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-- pragma synthesis_on
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-- pragma synthesis_on
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BEGIN
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BEGIN
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 latch
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-- HDL Embedded Text Block 1 latch
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-- latch 1
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-- latch 1
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PROCESS(clk)
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PROCESS(clk)
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BEGIN
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF RISING_EDGE(clk) THEN
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SIGN_out_stage1 <= SIGN_out_int;
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SIGN_out_stage1 <= SIGN_out_int;
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A_EXP <= A_EXP_int;
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A_EXP <= A_EXP_int;
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A_SIG <= A_SIG_int;
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A_SIG <= A_SIG_int;
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isINF_stage1 <= isINF_int;
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isINF_stage1 <= isINF_int;
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isNaN_stage1 <= isNaN_int;
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isNaN_stage1 <= isNaN_int;
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isZ_tab_stage1 <= isZ_tab_int;
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isZ_tab_stage1 <= isZ_tab_int;
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B_EXP <= B_EXP_int;
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B_EXP <= B_EXP_int;
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B_SIG <= B_SIG_int;
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B_SIG <= B_SIG_int;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- HDL Embedded Block 2 exceptions
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-- HDL Embedded Block 2 exceptions
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-- Non hierarchical truthtable
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-- Non hierarchical truthtable
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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exceptions_truth_process: PROCESS(A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
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exceptions_truth_process: PROCESS(A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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BEGIN
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BEGIN
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-- Block 1
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-- Block 1
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IF (A_isINF = '0') AND (A_isNaN = '0') AND (A_isZ = '0') AND (B_isINF = '0') AND (B_isNaN = '0') AND (B_isZ = '0') THEN
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IF (A_isINF = '0') AND (A_isNaN = '0') AND (A_isZ = '0') AND (B_isINF = '0') AND (B_isNaN = '0') AND (B_isZ = '0') THEN
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isZ_tab_int <= '0';
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isZ_tab_int <= '0';
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isINF_int <= '0';
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isINF_int <= '0';
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isNaN_int <= '0';
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isNaN_int <= '0';
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ELSIF (A_isINF = '1') AND (B_isZ = '1') THEN
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ELSIF (A_isINF = '1') AND (B_isZ = '1') THEN
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isZ_tab_int <= '0';
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isZ_tab_int <= '0';
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isINF_int <= '0';
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isINF_int <= '0';
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isNaN_int <= '1';
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isNaN_int <= '1';
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ELSIF (A_isZ = '1') AND (B_isINF = '1') THEN
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ELSIF (A_isZ = '1') AND (B_isINF = '1') THEN
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isZ_tab_int <= '0';
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isZ_tab_int <= '0';
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isINF_int <= '0';
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isINF_int <= '0';
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isNaN_int <= '1';
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isNaN_int <= '1';
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ELSIF (A_isINF = '1') THEN
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ELSIF (A_isINF = '1') THEN
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isZ_tab_int <= '0';
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isZ_tab_int <= '0';
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isINF_int <= '1';
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isINF_int <= '1';
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isNaN_int <= '0';
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isNaN_int <= '0';
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ELSIF (B_isINF = '1') THEN
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ELSIF (B_isINF = '1') THEN
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isZ_tab_int <= '0';
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isZ_tab_int <= '0';
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isINF_int <= '1';
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isINF_int <= '1';
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isNaN_int <= '0';
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isNaN_int <= '0';
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ELSIF (A_isNaN = '1') THEN
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ELSIF (A_isNaN = '1') THEN
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isZ_tab_int <= '0';
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isZ_tab_int <= '0';
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isINF_int <= '0';
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isINF_int <= '0';
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isNaN_int <= '1';
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isNaN_int <= '1';
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ELSIF (B_isNaN = '1') THEN
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ELSIF (B_isNaN = '1') THEN
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isZ_tab_int <= '0';
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isZ_tab_int <= '0';
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isINF_int <= '0';
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isINF_int <= '0';
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isNaN_int <= '1';
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isNaN_int <= '1';
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ELSIF (A_isZ = '1') THEN
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ELSIF (A_isZ = '1') THEN
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isZ_tab_int <= '1';
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isZ_tab_int <= '1';
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isINF_int <= '0';
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isINF_int <= '0';
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isNaN_int <= '0';
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isNaN_int <= '0';
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ELSIF (B_isZ = '1') THEN
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ELSIF (B_isZ = '1') THEN
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isZ_tab_int <= '1';
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isZ_tab_int <= '1';
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isINF_int <= '0';
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isINF_int <= '0';
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isNaN_int <= '0';
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isNaN_int <= '0';
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ELSE
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ELSE
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isZ_tab_int <= '0';
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isZ_tab_int <= '0';
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isINF_int <= '0';
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isINF_int <= '0';
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isNaN_int <= '0';
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isNaN_int <= '0';
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END IF;
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END IF;
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END PROCESS exceptions_truth_process;
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END PROCESS exceptions_truth_process;
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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-- ModuleWare code(v1.1) for instance 'I3' of 'xor'
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-- ModuleWare code(v1.1) for instance 'I3' of 'xor'
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SIGN_out_int <= A_SIGN XOR B_SIGN;
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SIGN_out_int <= A_SIGN XOR B_SIGN;
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-- Instance port mappings.
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-- Instance port mappings.
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I0 : UnpackFP
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I0 : UnpackFP
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PORT MAP (
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PORT MAP (
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FP => FP_A,
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FP => FP_A,
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SIG => A_SIG_int,
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SIG => A_SIG_int,
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EXP => A_EXP_int,
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EXP => A_EXP_int,
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SIGN => A_SIGN,
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SIGN => A_SIGN,
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isNaN => A_isNaN,
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isNaN => A_isNaN,
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isINF => A_isINF,
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isINF => A_isINF,
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isZ => A_isZ,
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isZ => A_isZ,
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isDN => OPEN
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isDN => OPEN
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);
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);
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I1 : UnpackFP
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I1 : UnpackFP
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PORT MAP (
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PORT MAP (
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FP => FP_B,
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FP => FP_B,
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SIG => B_SIG_int,
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SIG => B_SIG_int,
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EXP => B_EXP_int,
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EXP => B_EXP_int,
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SIGN => B_SIGN,
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SIGN => B_SIGN,
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isNaN => B_isNaN,
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isNaN => B_isNaN,
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isINF => B_isINF,
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isINF => B_isINF,
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isZ => B_isZ,
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isZ => B_isZ,
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isDN => OPEN
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isDN => OPEN
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);
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);
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END struct;
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END struct;
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