-- VHDL Entity HAVOC.FPmul_stage2.interface
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-- VHDL Entity HAVOC.FPmul_stage2.interface
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- 2003-2004. V1.0
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-- 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY FPmul_stage2 IS
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ENTITY FPmul_stage2 IS
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PORT(
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PORT(
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A_EXP : IN std_logic_vector (7 DOWNTO 0);
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A_EXP : IN std_logic_vector (7 DOWNTO 0);
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A_SIG : IN std_logic_vector (31 DOWNTO 0);
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A_SIG : IN std_logic_vector (31 DOWNTO 0);
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B_EXP : IN std_logic_vector (7 DOWNTO 0);
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B_EXP : IN std_logic_vector (7 DOWNTO 0);
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B_SIG : IN std_logic_vector (31 DOWNTO 0);
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B_SIG : IN std_logic_vector (31 DOWNTO 0);
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SIGN_out_stage1 : IN std_logic;
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SIGN_out_stage1 : IN std_logic;
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clk : IN std_logic;
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clk : IN std_logic;
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isINF_stage1 : IN std_logic;
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isINF_stage1 : IN std_logic;
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isNaN_stage1 : IN std_logic;
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isNaN_stage1 : IN std_logic;
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isZ_tab_stage1 : IN std_logic;
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isZ_tab_stage1 : IN std_logic;
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EXP_in : OUT std_logic_vector (7 DOWNTO 0);
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EXP_in : OUT std_logic_vector (7 DOWNTO 0);
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EXP_neg_stage2 : OUT std_logic;
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EXP_neg_stage2 : OUT std_logic;
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EXP_pos_stage2 : OUT std_logic;
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EXP_pos_stage2 : OUT std_logic;
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SIGN_out_stage2 : OUT std_logic;
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SIGN_out_stage2 : OUT std_logic;
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SIG_in : OUT std_logic_vector (27 DOWNTO 0);
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SIG_in : OUT std_logic_vector (27 DOWNTO 0);
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isINF_stage2 : OUT std_logic;
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isINF_stage2 : OUT std_logic;
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isNaN_stage2 : OUT std_logic;
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isNaN_stage2 : OUT std_logic;
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isZ_tab_stage2 : OUT std_logic
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isZ_tab_stage2 : OUT std_logic
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);
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);
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-- Declarations
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-- Declarations
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END FPmul_stage2 ;
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END FPmul_stage2 ;
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--
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--
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-- VHDL Architecture HAVOC.FPmul_stage2.struct
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-- VHDL Architecture HAVOC.FPmul_stage2.struct
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- Copyright 2003-2004. V1.0
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-- Copyright 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ARCHITECTURE struct OF FPmul_stage2 IS
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ARCHITECTURE struct OF FPmul_stage2 IS
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL EXP_in_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_in_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_neg_int : std_logic;
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SIGNAL EXP_neg_int : std_logic;
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SIGNAL EXP_pos_int : std_logic;
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SIGNAL EXP_pos_int : std_logic;
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SIGNAL SIG_in_int : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_in_int : std_logic_vector(27 DOWNTO 0);
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SIGNAL dout : std_logic;
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SIGNAL dout : std_logic;
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SIGNAL dout1 : std_logic_vector(7 DOWNTO 0);
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SIGNAL dout1 : std_logic_vector(7 DOWNTO 0);
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SIGNAL prod : std_logic_vector(63 DOWNTO 0);
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SIGNAL prod : std_logic_vector(63 DOWNTO 0);
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BEGIN
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BEGIN
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 sig
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-- HDL Embedded Text Block 1 sig
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-- eb1 1
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-- eb1 1
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SIG_in_int <= prod(47 DOWNTO 20);
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SIG_in_int <= prod(47 DOWNTO 20);
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-- HDL Embedded Text Block 2 inv
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-- HDL Embedded Text Block 2 inv
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-- eb5 5
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-- eb5 5
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EXP_in_int <= (NOT dout1(7)) & dout1(6 DOWNTO 0);
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EXP_in_int <= (NOT dout1(7)) & dout1(6 DOWNTO 0);
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-- HDL Embedded Text Block 3 latch
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-- HDL Embedded Text Block 3 latch
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-- eb2 2
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-- eb2 2
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PROCESS(clk)
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PROCESS(clk)
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BEGIN
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF RISING_EDGE(clk) THEN
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EXP_in <= EXP_in_int;
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EXP_in <= EXP_in_int;
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SIG_in <= SIG_in_int;
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SIG_in <= SIG_in_int;
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EXP_pos_stage2 <= EXP_pos_int;
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EXP_pos_stage2 <= EXP_pos_int;
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EXP_neg_stage2 <= EXP_neg_int;
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EXP_neg_stage2 <= EXP_neg_int;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- HDL Embedded Text Block 4 latch2
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-- HDL Embedded Text Block 4 latch2
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-- latch2 4
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-- latch2 4
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PROCESS(clk)
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PROCESS(clk)
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BEGIN
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF RISING_EDGE(clk) THEN
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isINF_stage2 <= isINF_stage1;
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isINF_stage2 <= isINF_stage1;
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isNaN_stage2 <= isNaN_stage1;
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isNaN_stage2 <= isNaN_stage1;
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isZ_tab_stage2 <= isZ_tab_stage1;
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isZ_tab_stage2 <= isZ_tab_stage1;
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SIGN_out_stage2 <= SIGN_out_stage1;
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SIGN_out_stage2 <= SIGN_out_stage1;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- HDL Embedded Text Block 5 eb1
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-- HDL Embedded Text Block 5 eb1
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-- exp_pos 5
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-- exp_pos 5
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EXP_pos_int <= A_EXP(7) AND B_EXP(7);
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EXP_pos_int <= A_EXP(7) AND B_EXP(7);
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-- EXP_neg_int <= NOT(A_EXP(7) OR B_EXP(7));
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-- EXP_neg_int <= NOT(A_EXP(7) OR B_EXP(7));
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EXP_neg_int <= '1' WHEN ( (A_EXP(7)='0' AND NOT (A_EXP=X"7F")) AND (B_EXP(7)='0' AND NOT (B_EXP=X"7F")) ) ELSE '0';
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EXP_neg_int <= '1' WHEN ( (A_EXP(7)='0' AND NOT (A_EXP=X"7F")) AND (B_EXP(7)='0' AND NOT (B_EXP=X"7F")) ) ELSE '0';
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-- ModuleWare code(v1.1) for instance 'I4' of 'add'
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-- ModuleWare code(v1.1) for instance 'I4' of 'add'
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I4combo: PROCESS (A_EXP, B_EXP, dout)
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I4combo: PROCESS (A_EXP, B_EXP, dout)
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VARIABLE mw_I4t0 : std_logic_vector(8 DOWNTO 0);
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VARIABLE mw_I4t0 : std_logic_vector(8 DOWNTO 0);
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VARIABLE mw_I4t1 : std_logic_vector(8 DOWNTO 0);
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VARIABLE mw_I4t1 : std_logic_vector(8 DOWNTO 0);
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VARIABLE mw_I4sum : unsigned(8 DOWNTO 0);
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VARIABLE mw_I4sum : unsigned(8 DOWNTO 0);
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VARIABLE mw_I4carry : std_logic;
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VARIABLE mw_I4carry : std_logic;
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BEGIN
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BEGIN
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mw_I4t0 := '0' & A_EXP;
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mw_I4t0 := '0' & A_EXP;
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mw_I4t1 := '0' & B_EXP;
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mw_I4t1 := '0' & B_EXP;
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mw_I4carry := dout;
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mw_I4carry := dout;
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mw_I4sum := unsigned(mw_I4t0) + unsigned(mw_I4t1) + mw_I4carry;
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mw_I4sum := unsigned(mw_I4t0) + unsigned(mw_I4t1) + mw_I4carry;
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dout1 <= conv_std_logic_vector(mw_I4sum(7 DOWNTO 0),8);
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dout1 <= conv_std_logic_vector(mw_I4sum(7 DOWNTO 0),8);
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END PROCESS I4combo;
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END PROCESS I4combo;
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-- ModuleWare code(v1.1) for instance 'I2' of 'mult'
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-- ModuleWare code(v1.1) for instance 'I2' of 'mult'
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I2combo : PROCESS (A_SIG, B_SIG)
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I2combo : PROCESS (A_SIG, B_SIG)
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VARIABLE dtemp : unsigned(63 DOWNTO 0);
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VARIABLE dtemp : unsigned(63 DOWNTO 0);
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BEGIN
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BEGIN
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dtemp := (unsigned(A_SIG) * unsigned(B_SIG));
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dtemp := (unsigned(A_SIG) * unsigned(B_SIG));
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prod <= std_logic_vector(dtemp);
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prod <= std_logic_vector(dtemp);
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END PROCESS I2combo;
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END PROCESS I2combo;
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-- ModuleWare code(v1.1) for instance 'I6' of 'vdd'
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-- ModuleWare code(v1.1) for instance 'I6' of 'vdd'
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dout <= '1';
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dout <= '1';
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-- Instance port mappings.
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-- Instance port mappings.
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END struct;
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END struct;
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