URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [port_blinker/] [1.0/] [ip_xact/] [port_blinker.1.0.xml] - Diff between revs 145 and 181

Rev 145	Rev 181
Line 3...	Line 3...

`TUT`	`TUT`
`ip.hwp.accelerator`	`ip.hwp.accelerator`
`port_blinker`	`port_blinker`
`1.0`	`1.0`
	`Counts up and inverts output when reaching the limit value. Then start over again.`


`clk`	`clk`


Line 156...	Line 157...
`IEEE.std_logic_1164.all`	`IEEE.std_logic_1164.all`
`rtl`	`rtl`








`ena_in`	`ena_in`

`in`	`in`
Line 173...	Line 177...
`IEEE.std_logic_1164.all`	`IEEE.std_logic_1164.all`
`rtl`	`rtl`








`port_out`	`port_out`

`out`	`out`
Line 190...	Line 197...
`IEEE.std_logic_1164.all`	`IEEE.std_logic_1164.all`
`rtl`	`rtl`








`rst_n`	`rst_n`

`in`	`in`
Line 207...	Line 217...
`IEEE.std_logic_1164.all`	`IEEE.std_logic_1164.all`
`rtl`	`rtl`








`val_in`	`val_in`

`in`	`in`
Line 224...	Line 237...
`IEEE.std_logic_1164.all`	`IEEE.std_logic_1164.all`
`rtl`	`rtl`










`SIGNAL_WIDTH`	`SIGNAL_WIDTH`
Line 242...	Line 258...

`../vhd/port_blinker.vhd`	`../vhd/port_blinker.vhd`
`vhdlSource`	`vhdlSource`
`false`	`false`
`work`	`work`

`false`



`vhdlSource`	`vhdlSource`
`vcom`	`vcom`
`-quiet -check_synthesis`	`-quiet -check_synthesis`
Line 261...	Line 274...
`documentation`	`documentation`

`../doc/port_blinker.html`	`../doc/port_blinker.html`
`documentation`	`documentation`
`false`	`false`

`false`



`../doc/TUT.ip.hwp.accelerator.port_blinker.1.0.png`	`../doc/TUT.ip.hwp.accelerator.port_blinker.1.0.png`
`jpg`	`jpg`
`false`	`false`

`false`




`Counts up and inverts output when reaching the limit value. Then start over again.`



`IP`	`IP`
`HW`	`HW`