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Line 4... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : ase_mesh1.vhdl
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-- File : ase_mesh1.vhdl
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-- Author : Lasse Lehtonen (ase)
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-- Author : Lasse Lehtonen (ase)
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-- Company :
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-- Company :
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-- Created : 2010-06-14
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-- Created : 2010-06-14
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-- Last update: 2011-12-02
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-- Last update: 2012-06-14
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-- Platform :
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-- Platform :
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-- Standard : VHDL'93
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description: Instantiate variable-sized network from rows*cols routers
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-- Description: Instantiate variable-sized network from rows*cols routers
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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| Line 23... |
Line 23... |
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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entity ase_mesh1 is
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entity ase_mesh1 is
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|
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generic (
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generic (
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n_rows_g : positive := 4; -- Nuber of rows
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n_rows_g : positive := 4; -- Number of rows
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n_cols_g : positive := 4; -- Nuber of columns
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n_cols_g : positive := 4; -- Number of columns
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cmd_width_g : positive := 2; -- Width of the cmd line in bits
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cmd_width_g : positive := 2; -- Width of the cmd line in bits
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bus_width_g : positive := 32 -- Width of the data bus in bits
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bus_width_g : positive := 32; -- Width of the data bus in bits
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fifo_depth_g : natural := 4
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
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| Line 46... |
Line 47... |
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architecture structural of ase_mesh1 is
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architecture structural of ase_mesh1 is
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-- row data
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-- row data
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-- All signals amed as <source><destination>name,
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-- All signals named as <source><destination>name,
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-- e.g. sn_data means "data going from south to north"
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-- e.g. sn_data means "data going from south to north"
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type r_data_type is array (0 to n_rows_g) of
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type r_data_type is array (0 to n_rows_g*2-1) of
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std_logic_vector(n_cols_g*bus_width_g-1 downto 0);
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std_logic_vector(n_cols_g*bus_width_g-1 downto 0);
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type r_bit_type is array (0 to n_rows_g) of
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type r_cmd_type is array (0 to n_rows_g*2-1) of
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std_logic_vector(2*n_cols_g-1 downto 0);
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type r_bit_type is array (0 to n_rows_g*2-1) of
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std_logic_vector(n_cols_g-1 downto 0);
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std_logic_vector(n_cols_g-1 downto 0);
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signal sn_data : r_data_type;
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signal sn_data : r_data_type;
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signal sn_av : r_bit_type;
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signal sn_cmd : r_cmd_type;
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signal sn_da : r_bit_type;
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signal sn_stall : r_bit_type;
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signal sn_stall : r_bit_type;
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signal ns_data : r_data_type;
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signal ns_data : r_data_type;
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signal ns_av : r_bit_type;
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signal ns_cmd : r_cmd_type;
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signal ns_da : r_bit_type;
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signal ns_stall : r_bit_type;
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signal ns_stall : r_bit_type;
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-- col data
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-- col data
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type c_data_type is array (0 to n_cols_g) of
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type c_data_type is array (0 to n_cols_g*2-1) of
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std_logic_vector(n_rows_g*bus_width_g-1 downto 0);
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std_logic_vector(n_rows_g*bus_width_g-1 downto 0);
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type c_bit_type is array (0 to n_cols_g) of
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type c_cmd_type is array (0 to n_cols_g*2-1) of
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std_logic_vector(2*n_rows_g-1 downto 0);
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type c_bit_type is array (0 to n_cols_g*2-1) of
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std_logic_vector(n_rows_g-1 downto 0);
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std_logic_vector(n_rows_g-1 downto 0);
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signal ew_data : c_data_type;
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signal ew_data : c_data_type;
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signal ew_av : c_bit_type;
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signal ew_cmd : c_cmd_type;
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signal ew_da : c_bit_type;
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signal ew_stall : c_bit_type;
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signal ew_stall : c_bit_type;
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signal we_data : c_data_type;
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signal we_data : c_data_type;
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signal we_av : c_bit_type;
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signal we_cmd : c_cmd_type;
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signal we_da : c_bit_type;
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signal we_stall : c_bit_type;
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signal we_stall : c_bit_type;
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begin -- architecture structural
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begin -- architecture structural
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-- De-activate the signals "coming from outside"
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-- De-activate the signals "coming from outside"
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ns_data(0) <= (others => '0');
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ns_data(0) <= (others => '0');
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ns_av(0) <= (others => '0');
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ns_cmd(0) <= (others => '0');
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ns_da(0) <= (others => '0');
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ns_stall(n_rows_g*2-1) <= (others => '0');
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ns_stall(n_rows_g) <= (others => '0');
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we_data(0) <= (others => '0');
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we_data(0) <= (others => '0');
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we_av(0) <= (others => '0');
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we_cmd(0) <= (others => '0');
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we_da(0) <= (others => '0');
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we_stall(n_cols_g*2-1) <= (others => '0');
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we_stall(n_cols_g) <= (others => '0');
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sn_data(n_rows_g*2-1) <= (others => '0');
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sn_data(n_rows_g) <= (others => '0');
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sn_cmd(n_rows_g*2-1) <= (others => '0');
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sn_av(n_rows_g) <= (others => '0');
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sn_da(n_rows_g) <= (others => '0');
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sn_stall(0) <= (others => '0');
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sn_stall(0) <= (others => '0');
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ew_data(n_cols_g) <= (others => '0');
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ew_data(n_cols_g*2-1) <= (others => '0');
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ew_av(n_cols_g) <= (others => '0');
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ew_cmd(n_cols_g*2-1) <= (others => '0');
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ew_da(n_cols_g) <= (others => '0');
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ew_stall(0) <= (others => '0');
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ew_stall(0) <= (others => '0');
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-- Instantiate rows*cols routers
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-- Instantiate rows*cols routers
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row : for r in 0 to n_rows_g-1 generate
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row : for r in 0 to n_rows_g-1 generate
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col : for c in 0 to n_cols_g-1 generate
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col : for c in 0 to n_cols_g-1 generate
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col_fifo : if r < n_rows_g-1 generate
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ns_link_fifo : entity work.link_fifo
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generic map (
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cmd_width_g => cmd_width_g,
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data_width_g => bus_width_g,
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depth_g => fifo_depth_g)
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port map (
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clk => clk,
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rst_n => rst_n,
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cmd_in => ns_cmd(r*2+1)(c*2+1 downto c*2),
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data_in => ns_data(r*2+1)((c+1)*bus_width_g-1 downto c*bus_width_g),
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stall_out => ns_stall(r*2+1)(c),
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cmd_out => ns_cmd((r+1)*2)(c*2+1 downto c*2),
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data_out => ns_data((r+1)*2)((c+1)*bus_width_g-1 downto c*bus_width_g),
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stall_in => ns_stall((r+1)*2)(c));
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sn_link_fifo : entity work.link_fifo
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generic map (
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cmd_width_g => cmd_width_g,
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data_width_g => bus_width_g,
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depth_g => fifo_depth_g)
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port map (
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clk => clk,
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rst_n => rst_n,
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cmd_in => sn_cmd((r+1)*2)(c*2+1 downto c*2),
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data_in => sn_data((r+1)*2)((c+1)*bus_width_g-1 downto c*bus_width_g),
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stall_out => sn_stall((r+1)*2)(c),
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cmd_out => sn_cmd((r)*2+1)(c*2+1 downto c*2),
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data_out => sn_data((r)*2+1)((c+1)*bus_width_g-1 downto c*bus_width_g),
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stall_in => sn_stall((r)*2+1)(c));
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end generate col_fifo;
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row_fifo : if c < n_cols_g-1 generate
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we_link_fifo : entity work.link_fifo
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generic map (
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cmd_width_g => cmd_width_g,
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data_width_g => bus_width_g,
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depth_g => fifo_depth_g)
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port map (
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clk => clk,
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rst_n => rst_n,
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cmd_in => we_cmd(c*2+1)(r*2+1 downto r*2),
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data_in => we_data(c*2+1)((r+1)*bus_width_g-1 downto r*bus_width_g),
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stall_out => we_stall(c*2+1)(r),
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cmd_out => we_cmd((c+1)*2)(r*2+1 downto r*2),
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data_out => we_data((c+1)*2)((r+1)*bus_width_g-1 downto r*bus_width_g),
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stall_in => we_stall((c+1)*2)(r));
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ew_link_fifo : entity work.link_fifo
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generic map (
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cmd_width_g => cmd_width_g,
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data_width_g => bus_width_g,
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depth_g => fifo_depth_g)
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port map (
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clk => clk,
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rst_n => rst_n,
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cmd_in => ew_cmd((c+1)*2)(r*2+1 downto r*2),
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data_in => ew_data((c+1)*2)((r+1)*bus_width_g-1 downto r*bus_width_g),
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stall_out => ew_stall((c+1)*2)(r),
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cmd_out => ew_cmd((c)*2+1)(r*2+1 downto r*2),
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data_out => ew_data((c)*2+1)((r+1)*bus_width_g-1 downto r*bus_width_g),
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stall_in => ew_stall((c)*2+1)(r));
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end generate row_fifo;
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i_router : entity work.ase_mesh1_router(rtl)
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i_router : entity work.ase_mesh1_router(rtl)
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generic map (
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generic map (
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n_rows_g => n_rows_g,
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n_rows_g => n_rows_g,
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n_cols_g => n_cols_g,
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n_cols_g => n_cols_g,
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bus_width_g => bus_width_g)
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bus_width_g => bus_width_g)
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| Line 128... |
Line 188... |
((r*n_cols_g)+c)*bus_width_g),
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((r*n_cols_g)+c)*bus_width_g),
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a_da_out => cmd_out(2*((r*n_cols_g)+c)+1),
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a_da_out => cmd_out(2*((r*n_cols_g)+c)+1),
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a_av_out => cmd_out(2*((r*n_cols_g)+c)),
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a_av_out => cmd_out(2*((r*n_cols_g)+c)),
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a_stall_in => stall_in((r*n_cols_g)+c),
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a_stall_in => stall_in((r*n_cols_g)+c),
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n_data_in => ns_data(r)((c+1)*bus_width_g-1 downto c*bus_width_g),
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n_data_in => ns_data(r*2)((c+1)*bus_width_g-1 downto c*bus_width_g),
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n_da_in => ns_da(r)(c),
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n_da_in => ns_cmd(r*2)(c*2),
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n_av_in => ns_av(r)(c),
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n_av_in => ns_cmd(r*2)(c*2+1),
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n_stall_out => ns_stall(r)(c),
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n_stall_out => ns_stall(r*2)(c),
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n_data_out => sn_data(r)((c+1)*bus_width_g-1 downto c*bus_width_g),
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n_data_out => sn_data(r*2)((c+1)*bus_width_g-1 downto c*bus_width_g),
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n_da_out => sn_da(r)(c),
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n_da_out => sn_cmd(r*2)(c*2),
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n_av_out => sn_av(r)(c),
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n_av_out => sn_cmd(r*2)(c*2+1),
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n_stall_in => sn_stall(r)(c),
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n_stall_in => sn_stall(r*2)(c),
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e_data_in => ew_data(c+1)((r+1)*bus_width_g-1 downto r*bus_width_g),
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e_data_in => ew_data(c*2+1)((r+1)*bus_width_g-1 downto r*bus_width_g),
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e_da_in => ew_da(c+1)(r),
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e_da_in => ew_cmd(c*2+1)(r*2),
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e_av_in => ew_av(c+1)(r),
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e_av_in => ew_cmd(c*2+1)(r*2+1),
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e_stall_out => ew_stall(c+1)(r),
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e_stall_out => ew_stall(c*2+1)(r),
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e_data_out => we_data(c+1)((r+1)*bus_width_g-1 downto r*bus_width_g),
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e_data_out => we_data(c*2+1)((r+1)*bus_width_g-1 downto r*bus_width_g),
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e_da_out => we_da(c+1)(r),
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e_da_out => we_cmd(c*2+1)(r*2),
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e_av_out => we_av(c+1)(r),
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e_av_out => we_cmd(c*2+1)(r*2+1),
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e_stall_in => we_stall(c+1)(r),
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e_stall_in => we_stall(c*2+1)(r),
|
|
|
s_data_in => sn_data(r+1)((c+1)*bus_width_g-1 downto c*bus_width_g),
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s_data_in => sn_data(r*2+1)((c+1)*bus_width_g-1 downto c*bus_width_g),
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s_da_in => sn_da(r+1)(c),
|
s_da_in => sn_cmd(r*2+1)(c*2),
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s_av_in => sn_av(r+1)(c),
|
s_av_in => sn_cmd(r*2+1)(c*2+1),
|
s_stall_out => sn_stall(r+1)(c),
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s_stall_out => sn_stall(r*2+1)(c),
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s_data_out => ns_data(r+1)((c+1)*bus_width_g-1 downto c*bus_width_g),
|
s_data_out => ns_data(r*2+1)((c+1)*bus_width_g-1 downto c*bus_width_g),
|
s_da_out => ns_da(r+1)(c),
|
s_da_out => ns_cmd(r*2+1)(c*2),
|
s_av_out => ns_av(r+1)(c),
|
s_av_out => ns_cmd(r*2+1)(c*2+1),
|
s_stall_in => ns_stall(r+1)(c),
|
s_stall_in => ns_stall(r*2+1)(c),
|
|
|
w_data_in => we_data(c)((r+1)*bus_width_g-1 downto r*bus_width_g),
|
w_data_in => we_data(c*2)((r+1)*bus_width_g-1 downto r*bus_width_g),
|
w_da_in => we_da(c)(r),
|
w_da_in => we_cmd(c*2)(r*2),
|
w_av_in => we_av(c)(r),
|
w_av_in => we_cmd(c*2)(r*2+1),
|
w_stall_out => we_stall(c)(r),
|
w_stall_out => we_stall(c*2)(r),
|
w_data_out => ew_data(c)((r+1)*bus_width_g-1 downto r*bus_width_g),
|
w_data_out => ew_data(c*2)((r+1)*bus_width_g-1 downto r*bus_width_g),
|
w_da_out => ew_da(c)(r),
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w_da_out => ew_cmd(c*2)(r*2),
|
w_av_out => ew_av(c)(r),
|
w_av_out => ew_cmd(c*2)(r*2+1),
|
w_stall_in => ew_stall(c)(r));
|
w_stall_in => ew_stall(c*2)(r));
|
|
|
end generate col;
|
end generate col;
|
end generate row;
|
end generate row;
|
|
|
|
|
