URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
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Rev 179 |
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../vhd/txt_util.vhd
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../vhd/txt_util.vhd
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vhdlSource
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vhdlSource
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false
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false
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work
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work
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false
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../vhd/basic_tester_pkg.vhd
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../vhd/basic_tester_pkg.vhd
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vhdlSource
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vhdlSource
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false
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false
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work
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work
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false
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../vhd/basic_tester_tx.vhd
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../vhd/basic_tester_tx.vhd
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vhdlSource
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vhdlSource
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false
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false
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work
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work
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false
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vhdlSource
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vhdlSource
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vcom
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vcom
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-check_synthesis
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-check_synthesis
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Line 320... |
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../tb/tb_basic_tester.vhd
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../tb/tb_basic_tester.vhd
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vhdlSource
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vhdlSource
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false
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false
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work
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work
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false
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Top-level. Generates clock and reset, instantiates basic tester tx+rx and hibi wrappers.
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Top-level. Generates clock and reset, instantiates basic tester tx+rx and hibi wrappers.
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../vhd/basic_tester_rx.vhd
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../vhd/basic_tester_rx.vhd
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vhdlSource
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vhdlSource
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false
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false
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work
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work
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false
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Receiver unit.
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Receiver unit.
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../sim/test_tx.txt
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../sim/test_tx.txt
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ASCII
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ASCII
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false
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false
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false
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Contents of transmitted values
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Contents of transmitted values
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../sim/compile_all.sh
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../sim/compile_all.sh
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shell script
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shell script
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false
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false
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false
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Creates VHDL libraries and compiles everything.
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Creates VHDL libraries and compiles everything.
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../sim/tb_basic_tester.do
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../sim/tb_basic_tester.do
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Modelsim macro
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Modelsim macro
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false
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false
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false
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Sets up the wave viewer
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Sets up the wave viewer
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../sim/test_rx.txt
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../sim/test_rx.txt
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ASCII
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ASCII
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false
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false
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false
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Expected values for the receiver
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Expected values for the receiver
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vhdlSource
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vhdlSource
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vcom
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vcom
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-check_synthesis
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-check_synthesis
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false
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false
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../../../../ip.hwp.storage/fifos
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../../../../ip.hwp.storage/fifos
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../../../../ip.hwp.storage/fifos/multi_clk/vhd
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../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd
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../../../hibi/3.0/vhd
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../../../hibi/3.0/vhd
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