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[/] [g729a_codec/] [trunk/] [VHDL/] [G729A_asip_mulu_pipeb.vhd] - Diff between revs 2 and 3

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Line 120... Line 120...
  end function;
  end function;
 
 
  signal PROD1,PROD2 : LDWORD_T;
  signal PROD1,PROD2 : LDWORD_T;
  signal MULA_RES : LDWORD_T;
  signal MULA_RES : LDWORD_T;
  signal MULA_RES_q : LDWORD_T;
  signal MULA_RES_q : LDWORD_T;
  signal MULA_OVF : std_logic;
 
  signal MULA_OVF_q : std_logic;
 
  signal LMUL_PROD_q : LDWORD_T;
  signal LMUL_PROD_q : LDWORD_T;
  signal LMUL_RES : LDWORD_T;
  signal LMUL_RES : LDWORD_T;
  signal LMUL_OVF : std_logic;
  signal LMUL_OVF : std_logic;
  signal MULR_PROD_q,MULR_SUM1,MULR_SUM2 : LDWORD_T;
  signal MULR_PROD_q,MULR_SUM1,MULR_SUM2 : LDWORD_T;
  signal MULR_RES : LDWORD_T;
  signal MULR_RES : LDWORD_T;
Line 166... Line 164...
  -- for address arithmetic.
  -- for address arithmetic.
 
 
  MULA_RES(SDLEN-1 downto 0) <= PROD1(SDLEN-1 downto 0);
  MULA_RES(SDLEN-1 downto 0) <= PROD1(SDLEN-1 downto 0);
  MULA_RES(LDLEN-1 downto SDLEN) <= (others => '0');
  MULA_RES(LDLEN-1 downto SDLEN) <= (others => '0');
 
 
  MULA_OVF <= '0';
 
 
 
  -- pipe register
  -- pipe register
  process(CLK_i)
  process(CLK_i)
  begin
  begin
    if(CLK_i = '1' and CLK_i'event) then
    if(CLK_i = '1' and CLK_i'event) then
      MULA_RES_q <= MULA_RES;
      MULA_RES_q <= MULA_RES;
      MULA_OVF_q <= MULA_OVF;
 
    end if;
    end if;
  end process;
  end process;
 
 
--  ------------------------------------
--  ------------------------------------
--  -- L_mac() & L_msu()
--  -- L_mac() & L_msu()
Line 446... Line 441...
    end if;
    end if;
  end process;
  end process;
 
 
  --process(CTRL_q,MAC_RES_q,MAC_OVF_q,MULR_RES,MULR_OVF,LMUL_RES,LMUL_OVF,
  --process(CTRL_q,MAC_RES_q,MAC_OVF_q,MULR_RES,MULR_OVF,LMUL_RES,LMUL_OVF,
  --  M3216_RES,M3216_OVF)
  --  M3216_RES,M3216_OVF)
  process(CTRL_q,MULA_RES_q,MULA_OVF_q,MULR_RES,MULR_OVF,LMUL_RES,LMUL_OVF,
  process(CTRL_q,MULA_RES_q,MULR_RES,MULR_OVF,LMUL_RES,LMUL_OVF,
    M3216_RES,M3216_OVF)
    M3216_RES,M3216_OVF)
  begin
  begin
    case CTRL_q is
    case CTRL_q is
      when MC_MULA =>
      when MC_MULA =>
        RES_o <= MULA_RES_q;
        RES_o <= MULA_RES_q;
        OVF_o <= MULA_OVF_q;
        OVF_o <= '0';
      --when MC_LMAC|MC_LMSU =>
      --when MC_LMAC|MC_LMSU =>
      --  RES_o <= MAC_RES;
      --  RES_o <= MAC_RES;
      --  OVF_o <= MAC_OVF;
      --  OVF_o <= MAC_OVF;
      when MC_MULR =>
      when MC_MULR =>
        RES_o <= MULR_RES;
        RES_o <= MULR_RES;

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