OpenCores
URL https://opencores.org/ocsvn/g729a_codec/g729a_codec/trunk

Subversion Repositories g729a_codec

[/] [g729a_codec/] [trunk/] [VHDL/] [G729A_asip_spc.vhd] - Diff between revs 2 and 3

Show entire file | Details | Blame | View Log

Rev 2 Rev 3
Line 92... Line 92...
 
 
  constant IO_NONE : std_logic_vector(2-1 downto 0) := "00";
  constant IO_NONE : std_logic_vector(2-1 downto 0) := "00";
  constant IO_READ : std_logic_vector(2-1 downto 0) := "01";
  constant IO_READ : std_logic_vector(2-1 downto 0) := "01";
  constant IO_WRITE : std_logic_vector(2-1 downto 0) := "10";
  constant IO_WRITE : std_logic_vector(2-1 downto 0) := "10";
 
 
 
  constant MAX_IO_COUNT : natural := 2048;
 
 
  -- sequencer "instruction" type
  -- sequencer "instruction" type
 
 
  type PROG_T is record
  type PROG_T is record
    -- sub-program starting address
    -- sub-program starting address
    SADR : natural range 0 to 65536-1;
    SADR : natural range 0 to 65536-1;
    -- I/O mode selector
    -- I/O mode selector
    IO_MODE : std_logic_vector(2-1 downto 0);
    IO_MODE : std_logic_vector(2-1 downto 0);
    -- number of words to transfer when in read/write mode
    -- number of words to transfer when in read/write mode
    IO_COUNT : natural range 0 to 2048-1;
    IO_COUNT : natural range 0 to MAX_IO_COUNT-1;
    -- I/O address selector
    -- I/O address selector
    IO_ASEL : std_logic_vector(3-1 downto 0);
    IO_ASEL : std_logic_vector(3-1 downto 0);
    -- halt when sub-program ends
    -- halt when sub-program ends
    HALT : std_logic;
    HALT : std_logic;
  end record;
  end record;
Line 128... Line 130...
  --
  --
  -- Sub-programs "a" and "b" are mutually exclusive: "a" must
  -- Sub-programs "a" and "b" are mutually exclusive: "a" must
  -- be used before encoding/decoding the first packet of a  
  -- be used before encoding/decoding the first packet of a  
  -- conversation, while "b" must be used on following packets.
  -- conversation, while "b" must be used on following packets.
 
 
  constant PROG_SEQ_q : PROG_SEQ_T(0 to 40-1) := (
  constant MAX_PROG : natural := 40;
 
 
 
  constant PROG_SEQ_q : PROG_SEQ_T(0 to MAX_PROG-1) := (
    --
    --
    -- "init only" sub-program
    -- "init only" sub-program
    --
    --
    (INIT_DEC,IO_NONE,0,"000",'0'),
    (INIT_DEC,IO_NONE,0,"000",'0'),
    (INIT_COD,IO_NONE,0,"000",'1'),
    (INIT_COD,IO_NONE,0,"000",'1'),
Line 213... Line 217...
    TS_WAIT5,
    TS_WAIT5,
    TS_WAIT6
    TS_WAIT6
  );
  );
 
 
  signal TS,TS_q : TEST_STATE_T;
  signal TS,TS_q : TEST_STATE_T;
  signal PROG_CNT_q : natural;
  signal PROG_CNT_q : natural range 0 to MAX_PROG-1;
  signal PROG_FIRST : natural;
  signal PROG_FIRST : natural range 0 to MAX_PROG-1;
  signal PROG_NEXT : std_logic;
  signal PROG_NEXT : std_logic;
  signal PROG_LAST : std_logic;
  signal PROG_LAST : std_logic;
  signal IO_MODE : std_logic_vector(2-1 downto 0);
  signal IO_MODE : std_logic_vector(2-1 downto 0);
  signal IO_COUNT : natural;
  signal IO_COUNT : natural range 0 to MAX_IO_COUNT-1;
  signal IO_ASEL : std_logic_vector(3-1 downto 0);
  signal IO_ASEL : std_logic_vector(3-1 downto 0);
  signal A_STRT,A_STRT_q : std_logic;
  signal A_STRT,A_STRT_q : std_logic;
  signal D_STRT,D_STRT_q : std_logic;
  signal D_STRT,D_STRT_q : std_logic;
  signal BSY,BSY_q : std_logic;
  signal BSY,BSY_q : std_logic;
  signal D_WE : std_logic;
  signal D_WE : std_logic;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.