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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: helperComponents
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-- Entity: helperComponents
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-- Date:2011-11-10
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-- Date:2011-11-10
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-- Author: Administrator
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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package helperComponents is
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package helperComponents is
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component gpibReader is
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component gpibReader is
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port (
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port (
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-- clock
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-- clock
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clk : in std_logic;
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clk : in std_logic;
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-- reset
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-- reset
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reset : std_logic;
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reset : std_logic;
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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------ GPIB interface --------------------------------------------------
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------ GPIB interface --------------------------------------------------
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- input data
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-- input data
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data_in : in std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0);
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-- data valid
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-- data valid
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dvd : in std_logic;
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dvd : in std_logic;
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-- listener active
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-- listener active
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lac : in std_logic;
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lac : in std_logic;
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-- last byte
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-- last byte
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lsb : in std_logic;
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lsb : in std_logic;
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-- ready to next byte
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-- ready to next byte
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rdy : out std_logic;
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rdy : out std_logic;
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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------ external interface ----------------------------------------------
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------ external interface ----------------------------------------------
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- is LE function active
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-- is LE function active
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isLE : in std_logic;
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isLE : in std_logic;
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-- current secondary address
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-- current secondary address
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secAddr : in std_logic_vector (4 downto 0);
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secAddr : in std_logic_vector (4 downto 0);
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-- secondary address of data
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-- secondary address of data
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dataSecAddr : out std_logic_vector (4 downto 0);
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dataSecAddr : out std_logic_vector (4 downto 0);
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-- buffer ready interrupt
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-- buffer ready interrupt
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buf_interrupt : out std_logic;
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buf_interrupt : out std_logic;
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-- indicates end of stream
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-- indicates end of stream
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end_of_stream : out std_logic;
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end_of_stream : out std_logic;
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-- resets reader
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-- resets reader
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reset_reader : in std_logic;
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reset_reader : in std_logic;
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------------------ fifo --------------------------------------
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------------------ fifo --------------------------------------
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-- indicates fifo full
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-- indicates fifo full
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fifo_full : in std_logic;
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fifo_full : in std_logic;
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-- indicates fifo ready to write
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-- indicates fifo ready to write
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fifo_ready_to_write : in std_logic;
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fifo_ready_to_write : in std_logic;
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-- indicates at least one byte in fifo
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-- indicates at least one byte in fifo
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at_least_one_byte_in_fifo : in std_logic;
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at_least_one_byte_in_fifo : in std_logic;
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-- output data
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-- output data
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data_out : out std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0);
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-- fifo strobe
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-- fifo strobe
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fifo_strobe : out std_logic
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fifo_strobe : out std_logic
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);
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);
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end component;
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end component;
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component gpibWriter is
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component gpibWriter is
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port (
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port (
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-- clock
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-- clock
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clk : in std_logic;
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clk : in std_logic;
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-- reset
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-- reset
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reset : std_logic;
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reset : std_logic;
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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------ GPIB interface --------------------------------------------------
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------ GPIB interface --------------------------------------------------
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- output data
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-- output data
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data_out : out std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0);
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-- wait for new cycle
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-- wait for new cycle
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wnc : in std_logic;
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wnc : in std_logic;
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-- seriall poll active
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-- seriall poll active
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spa : in std_logic;
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spa : in std_logic;
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-- new byte available
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-- new byte available
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nba : out std_logic;
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nba : out std_logic;
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-- end of string
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-- end of string
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endOf : out std_logic;
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endOf : out std_logic;
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-- talker active
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-- talker active
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tac : in std_logic;
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tac : in std_logic;
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-- controller write command
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-- controller write command
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cwrc : in std_logic;
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cwrc : in std_logic;
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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------ external interface ----------------------------------------------
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------ external interface ----------------------------------------------
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- TE is extended
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-- TE is extended
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isTE : in std_logic;
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isTE : in std_logic;
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-- current secondary address
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-- current secondary address
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secAddr : in std_logic_vector (4 downto 0);
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secAddr : in std_logic_vector (4 downto 0);
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-- secondary address of data
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-- secondary address of data
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dataSecAddr : in std_logic_vector (4 downto 0);
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dataSecAddr : in std_logic_vector (4 downto 0);
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-- buffer consumed
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-- buffer consumed
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buf_interrupt : out std_logic;
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buf_interrupt : out std_logic;
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-- indicates end of stream
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-- indicates end of stream
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end_of_stream : in std_logic;
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end_of_stream : in std_logic;
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-- resets writer
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-- resets writer
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reset_writer : in std_logic;
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reset_writer : in std_logic;
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-- enables writer
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-- enables writer
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writer_enable : in std_logic;
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writer_enable : in std_logic;
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---------------- fifo ---------------------------
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---------------- fifo ---------------------------
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availableFifoBytesCount : in std_logic_vector(10 downto 0);
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availableFifoBytesCount : in std_logic_vector(10 downto 0);
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-- fifo read strobe
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-- fifo read strobe
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fifo_read_strobe : out std_logic;
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fifo_read_strobe : out std_logic;
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-- indicates fifo ready to read
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-- indicates fifo ready to read
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fifo_ready_to_read : in std_logic;
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fifo_ready_to_read : in std_logic;
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-- input data
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-- input data
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fifo_data_in : in std_logic_vector (7 downto 0)
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fifo_data_in : in std_logic_vector (7 downto 0)
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);
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);
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end component;
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end component;
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component SerialPollCoordinator is
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component SerialPollCoordinator is
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port (
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port (
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-- clock
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-- clock
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clk : in std_logic;
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clk : in std_logic;
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-- reset
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-- reset
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reset : in std_logic;
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reset : in std_logic;
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-- data accepted
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-- data accepted
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DAC : in std_logic;
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DAC : in std_logic;
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-- receive status byte
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-- receive status byte
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rec_stb : in std_logic;
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rec_stb : in std_logic;
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-- attention in
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-- attention in
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ATN_in : in std_logic;
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ATN_in : in std_logic;
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-- attention out
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-- attention out
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ATN_out : out std_logic;
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ATN_out : out std_logic;
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-- output valid in
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-- output valid in
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output_valid_in : in std_logic;
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output_valid_in : in std_logic;
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-- output valid out
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-- output valid out
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output_valid_out : out std_logic;
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output_valid_out : out std_logic;
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-- stb received
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-- stb received
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stb_received : out std_logic
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stb_received : out std_logic
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);
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);
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end component;
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end component;
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component MemoryBlock is
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component MemoryBlock is
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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-------------------------------------------------
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-------------------------------------------------
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p1_addr : in std_logic_vector(10 downto 0);
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p1_addr : in std_logic_vector(10 downto 0);
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p1_data_in : in std_logic_vector(7 downto 0);
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p1_data_in : in std_logic_vector(7 downto 0);
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p1_strobe : in std_logic;
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p1_strobe : in std_logic;
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p1_data_out : out std_logic_vector(7 downto 0);
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p1_data_out : out std_logic_vector(7 downto 0);
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-------------------------------------------------
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-------------------------------------------------
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p2_addr : in std_logic_vector(10 downto 0);
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p2_addr : in std_logic_vector(10 downto 0);
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p2_data_in : in std_logic_vector(7 downto 0);
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p2_data_in : in std_logic_vector(7 downto 0);
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p2_strobe : in std_logic;
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p2_strobe : in std_logic;
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p2_data_out : out std_logic_vector(7 downto 0)
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p2_data_out : out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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component Fifo8b is
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component Fifo8b is
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generic (
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generic (
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MAX_ADDR_BIT_NUM : integer := 10
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MAX_ADDR_BIT_NUM : integer := 10
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);
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);
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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-------------- fifo --------------------
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-------------- fifo --------------------
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bytesAvailable : out std_logic;
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bytesAvailable : out std_logic;
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availableBytesCount : out std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
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availableBytesCount : out std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
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bufferFull : out std_logic;
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bufferFull : out std_logic;
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resetFifo : in std_logic;
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resetFifo : in std_logic;
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----------------------------------------
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----------------------------------------
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data_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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ready_to_write :out std_logic;
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ready_to_write :out std_logic;
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strobe_write : in std_logic;
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strobe_write : in std_logic;
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----------------------------------------
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----------------------------------------
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data_out : out std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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ready_to_read : out std_logic;
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ready_to_read : out std_logic;
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strobe_read : in std_logic
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strobe_read : in std_logic
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);
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);
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end component;
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end component;
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component Clk2x is
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component Clk2x is
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port (
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port (
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reset: in std_logic;
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reset: in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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clk2x : out std_logic
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clk2x : out std_logic
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);
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);
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end component;
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end component;
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component SinglePulseGenerator is
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component SinglePulseGenerator is
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generic (
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generic (
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WIDTH : integer := 3
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WIDTH : integer := 3
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);
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);
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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t_in: in std_logic;
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t_in: in std_logic;
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t_out : out std_logic;
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t_out : out std_logic;
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pulse : out std_logic
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pulse : out std_logic
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);
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);
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end component;
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end component;
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component EdgeDetector is
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component EdgeDetector is
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generic (
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generic (
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RISING : std_logic := '1';
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RISING : std_logic := '1';
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FALLING : std_logic := '0';
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FALLING : std_logic := '0';
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PULSE_WIDTH : integer := 10
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PULSE_WIDTH : integer := 10
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);
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);
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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in_data : in std_logic;
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in_data : in std_logic;
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pulse : out std_logic
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pulse : out std_logic
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);
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);
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end component;
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end component;
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component EventMem is
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component EventMem is
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port (
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port (
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reset : std_logic;
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reset : std_logic;
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-- event occured
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-- event occured
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occured : in std_logic;
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occured : in std_logic;
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-- event approved
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-- event approved
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approved : in std_logic;
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approved : in std_logic;
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-- output
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-- output
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output : out std_logic
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output : out std_logic
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);
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);
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end component;
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end component;
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component GpibSynchronizer is
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component GpibSynchronizer is
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port (
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port (
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-- clk
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-- clk
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clk : std_logic;
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clk : std_logic;
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-- DIO
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-- DIO
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DI : in std_logic_vector (7 downto 0);
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DI : in std_logic_vector (7 downto 0);
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DO : out std_logic_vector (7 downto 0);
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DO : out std_logic_vector (7 downto 0);
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-- attention
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-- attention
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ATN_in : in std_logic;
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ATN_in : in std_logic;
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ATN_out : out std_logic;
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ATN_out : out std_logic;
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-- data valid
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-- data valid
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DAV_in : in std_logic;
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DAV_in : in std_logic;
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DAV_out : out std_logic;
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DAV_out : out std_logic;
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-- not ready for data
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-- not ready for data
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NRFD_in : in std_logic;
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NRFD_in : in std_logic;
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NRFD_out : out std_logic;
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NRFD_out : out std_logic;
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-- no data accepted
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-- no data accepted
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NDAC_in : in std_logic;
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NDAC_in : in std_logic;
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NDAC_out : out std_logic;
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NDAC_out : out std_logic;
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-- end or identify
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-- end or identify
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EOI_in : in std_logic;
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EOI_in : in std_logic;
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EOI_out : out std_logic;
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EOI_out : out std_logic;
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-- service request
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-- service request
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SRQ_in : in std_logic;
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SRQ_in : in std_logic;
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SRQ_out : out std_logic;
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SRQ_out : out std_logic;
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-- interface clear
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-- interface clear
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IFC_in : in std_logic;
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IFC_in : in std_logic;
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IFC_out : out std_logic;
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IFC_out : out std_logic;
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-- remote enable
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-- remote enable
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REN_in : in std_logic;
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REN_in : in std_logic;
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REN_out : out std_logic
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REN_out : out std_logic
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);
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);
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end component;
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end component;
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end helperComponents;
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end helperComponents;
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