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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [common/] [utilPkg.vhd] - Diff between revs 3 and 13

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Rev 3 Rev 13
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--This file is part of fpga_gpib_controller.
 
--
 
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
 
-- it under the terms of the GNU General Public License as published by
 
-- the Free Software Foundation, either version 3 of the License, or
 
-- (at your option) any later version.
 
--
 
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
-- GNU General Public License for more details.
 
 
 
-- You should have received a copy of the GNU General Public License
 
-- along with Fpga_gpib_controller.  If not, see <http://www.gnu.org/licenses/>.
 
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-- Entity:      utilPkg
-- Entity:      utilPkg
-- Date:        2011-10-09  
-- Date:        2011-10-09  
-- Author:      apaluch
-- Author: Andrzej Paluch
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library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
 
 
package utilPkg is
package utilPkg is
 
 
        -- converts boolean to std_logic '0' or '1'
        -- converts boolean to std_logic '0' or '1'
        function to_stdl(b : boolean) return std_logic;
        function to_stdl(b : boolean) return std_logic;
 
 
        -- converts std_logic to boolean
        -- converts std_logic to boolean
        function is_1(v : std_logic) return boolean;
        function is_1(v : std_logic) return boolean;
 
 
end;
end;
 
 
package body utilPkg is
package body utilPkg is
 
 
        function to_stdl(b : boolean) return std_logic is begin
        function to_stdl(b : boolean) return std_logic is begin
                if b then
                if b then
                        return '1';
                        return '1';
                else
                else
                        return '0';
                        return '0';
                end if;
                end if;
        end function;
        end function;
 
 
        function is_1(v : std_logic) return boolean is begin
        function is_1(v : std_logic) return boolean is begin
                if v = '1' then
                if v = '1' then
                        return true;
                        return true;
                else
                else
                        return false;
                        return false;
                end if;
                end if;
        end function;
        end function;
 
 
 
 

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