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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company:
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-- Author: Andrzej Paluch
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-- Engineer:
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--
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--
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-- Create Date: 01:04:57 10/03/2011
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-- Create Date: 01:04:57 10/03/2011
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-- Design Name:
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-- Design Name:
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-- Module Name: if_func_PP - Behavioral
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-- Module Name: if_func_PP - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.utilPkg.all;
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use work.utilPkg.all;
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entity if_func_PP is
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entity if_func_PP is
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port(
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port(
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-- device inputs
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-- device inputs
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clk : in std_logic; -- clock
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clk : in std_logic; -- clock
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-- settings
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-- settings
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lpeUsed : std_logic;
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lpeUsed : std_logic;
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fixedPpLine : in std_logic_vector (2 downto 0);
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fixedPpLine : in std_logic_vector (2 downto 0);
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-- local commands
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-- local commands
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pon : in std_logic; -- power on
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pon : in std_logic; -- power on
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lpe : in std_logic; -- local poll enable
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lpe : in std_logic; -- local poll enable
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ist : in std_logic; -- individual status
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ist : in std_logic; -- individual status
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-- state inputs
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-- state inputs
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ACDS : in std_logic; -- accept data state
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ACDS : in std_logic; -- accept data state
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LADS : in std_logic; -- listener address state (L or LE)
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LADS : in std_logic; -- listener address state (L or LE)
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-- data input
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-- data input
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dio_data : in std_logic_vector(3 downto 0); -- byte from data lines
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dio_data : in std_logic_vector(3 downto 0); -- byte from data lines
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-- remote command inputs
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-- remote command inputs
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IDY : in std_logic; -- identify
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IDY : in std_logic; -- identify
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PPE : in std_logic; -- parallel poll enable
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PPE : in std_logic; -- parallel poll enable
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PPD : in std_logic; -- parallel poll disable
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PPD : in std_logic; -- parallel poll disable
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PPC : in std_logic; -- parallel poll configure
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PPC : in std_logic; -- parallel poll configure
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PPU : in std_logic; -- parallel poll unconfigure
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PPU : in std_logic; -- parallel poll unconfigure
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PCG : in std_logic; -- primary command group
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PCG : in std_logic; -- primary command group
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-- remote command outputs
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-- remote command outputs
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PPR : out std_logic; -- paralel poll response
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PPR : out std_logic; -- paralel poll response
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-- PPR command data
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-- PPR command data
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ppBitValue : out std_logic; -- bit value
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ppBitValue : out std_logic; -- bit value
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ppLineNumber : out std_logic_vector (2 downto 0);
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ppLineNumber : out std_logic_vector (2 downto 0);
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-- reported states
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-- reported states
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PPAS : out std_logic -- parallel poll active state
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PPAS : out std_logic -- parallel poll active state
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);
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);
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end if_func_PP;
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end if_func_PP;
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architecture Behavioral of if_func_PP is
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architecture Behavioral of if_func_PP is
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-- states
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-- states
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type PP_STATE_1 is (
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type PP_STATE_1 is (
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-- parallel poll idle state
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-- parallel poll idle state
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ST_PPIS,
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ST_PPIS,
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-- parallel poll standby state
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-- parallel poll standby state
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ST_PPSS,
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ST_PPSS,
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-- parallel poll active state
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-- parallel poll active state
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ST_PPAS
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ST_PPAS
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);
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);
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-- states
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-- states
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type PP_STATE_2 is (
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type PP_STATE_2 is (
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-- parallel poll unaddressed to configure state
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-- parallel poll unaddressed to configure state
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ST_PUCS,
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ST_PUCS,
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-- parallel poll addressed to configure state
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-- parallel poll addressed to configure state
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ST_PACS
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ST_PACS
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);
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);
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-- current state
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-- current state
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signal current_state_1 : PP_STATE_1;
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signal current_state_1 : PP_STATE_1;
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signal current_state_2 : PP_STATE_2;
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signal current_state_2 : PP_STATE_2;
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-- predicates
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-- predicates
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signal pred1, pred2, pred3, pred4, pred5 : boolean;
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signal pred1, pred2, pred3, pred4, pred5 : boolean;
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-- memorized PP metadata
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-- memorized PP metadata
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signal S : std_logic;
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signal S : std_logic;
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signal lineAddr : std_logic_vector (2 downto 0);
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signal lineAddr : std_logic_vector (2 downto 0);
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begin
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begin
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-- state machine process - PP_STATE_1
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-- state machine process - PP_STATE_1
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process(pon, clk) begin
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process(pon, clk) begin
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if pon = '1' then
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if pon = '1' then
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current_state_1 <= ST_PPIS;
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current_state_1 <= ST_PPIS;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case current_state_1 is
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case current_state_1 is
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------------------
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------------------
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when ST_PPIS =>
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when ST_PPIS =>
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if pred1 then
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if pred1 then
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S <= dio_data(3);
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S <= dio_data(3);
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lineAddr <= dio_data(2 downto 0);
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lineAddr <= dio_data(2 downto 0);
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current_state_1 <= ST_PPSS;
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current_state_1 <= ST_PPSS;
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end if;
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end if;
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------------------
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------------------
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when ST_PPSS =>
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when ST_PPSS =>
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if pred3 then
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if pred3 then
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current_state_1 <= ST_PPAS;
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current_state_1 <= ST_PPAS;
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elsif pred2 then
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elsif pred2 then
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current_state_1 <= ST_PPIS;
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current_state_1 <= ST_PPIS;
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end if;
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end if;
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------------------
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------------------
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when ST_PPAS =>
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when ST_PPAS =>
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if not pred3 then
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if not pred3 then
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current_state_1 <= ST_PPSS;
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current_state_1 <= ST_PPSS;
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end if;
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end if;
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------------------
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------------------
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when others =>
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when others =>
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current_state_1 <= ST_PPIS;
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current_state_1 <= ST_PPIS;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-- state machine process - PP_STATE_2
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-- state machine process - PP_STATE_2
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process(pon, clk) begin
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process(pon, clk) begin
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if pon = '1' then
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if pon = '1' then
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current_state_2 <= ST_PUCS;
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current_state_2 <= ST_PUCS;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case current_state_2 is
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case current_state_2 is
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------------------
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------------------
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when ST_PUCS =>
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when ST_PUCS =>
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if pred4 then
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if pred4 then
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current_state_2 <= ST_PACS;
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current_state_2 <= ST_PACS;
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end if;
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end if;
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------------------
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------------------
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when ST_PACS =>
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when ST_PACS =>
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if pred5 then
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if pred5 then
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current_state_2 <= ST_PUCS;
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current_state_2 <= ST_PUCS;
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end if;
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end if;
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------------------
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------------------
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when others =>
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when others =>
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current_state_2 <= ST_PUCS;
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current_state_2 <= ST_PUCS;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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ppBitValue <= (not S xor ist) when lpeUsed='0' else ist;
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ppBitValue <= (not S xor ist) when lpeUsed='0' else ist;
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ppLineNumber <= lineAddr when lpeUsed='0' else fixedPpLine;
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ppLineNumber <= lineAddr when lpeUsed='0' else fixedPpLine;
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PPR <= to_stdl(current_state_1 = ST_PPAS);
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PPR <= to_stdl(current_state_1 = ST_PPAS);
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PPAS <= to_stdl(current_state_1 = ST_PPAS);
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PPAS <= to_stdl(current_state_1 = ST_PPAS);
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-- predicates
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-- predicates
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with lpeUsed select
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with lpeUsed select
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pred1 <=
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pred1 <=
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is_1(lpe) when '1',
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is_1(lpe) when '1',
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PPE='1' and current_state_2=ST_PACS and ACDS='1' when others;
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PPE='1' and current_state_2=ST_PACS and ACDS='1' when others;
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with lpeUsed select
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with lpeUsed select
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pred2 <=
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pred2 <=
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is_1(not lpe) when '1',
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is_1(not lpe) when '1',
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((PPD='1' and current_state_2=ST_PACS) or PPU='1') and ACDS='1'
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((PPD='1' and current_state_2=ST_PACS) or PPU='1') and ACDS='1'
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when others;
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when others;
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pred3 <= IDY='1';
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pred3 <= IDY='1';
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pred4 <= PPC='1' and LADS='1' and ACDS='1';
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pred4 <= PPC='1' and LADS='1' and ACDS='1';
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pred5 <= PCG='1' and PPC='0' and ACDS='1';
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pred5 <= PCG='1' and PPC='0' and ACDS='1';
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end Behavioral;
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end Behavioral;
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