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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: SerialPollCoordinator
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-- Entity: SerialPollCoordinator
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-- Date:2011-11-03
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-- Date:2011-11-03
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-- Author: Administrator
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity SerialPollCoordinator is
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entity SerialPollCoordinator is
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port (
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port (
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-- clock
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-- clock
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clk : in std_logic;
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clk : in std_logic;
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-- reset
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-- reset
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reset : in std_logic;
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reset : in std_logic;
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-- data accepted
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-- data accepted
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DAC : in std_logic;
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DAC : in std_logic;
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-- receive status byte
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-- receive status byte
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rec_stb : in std_logic;
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rec_stb : in std_logic;
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-- attention in
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-- attention in
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ATN_in : in std_logic;
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ATN_in : in std_logic;
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-- attention out
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-- attention out
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ATN_out : out std_logic;
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ATN_out : out std_logic;
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-- output valid in
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-- output valid in
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output_valid_in : in std_logic;
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output_valid_in : in std_logic;
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-- output valid out
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-- output valid out
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output_valid_out : out std_logic;
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output_valid_out : out std_logic;
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-- stb received
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-- stb received
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stb_received : out std_logic
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stb_received : out std_logic
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);
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);
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end SerialPollCoordinator;
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end SerialPollCoordinator;
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architecture arch of SerialPollCoordinator is
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architecture arch of SerialPollCoordinator is
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-- serial poll coordinator states
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-- serial poll coordinator states
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type SPC_STATE is (
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type SPC_STATE is (
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ST_IDLE,
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ST_IDLE,
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ST_WAIT_DAC,
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ST_WAIT_DAC,
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ST_WAIT_REC_STB_0
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ST_WAIT_REC_STB_0
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);
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);
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signal current_state : SPC_STATE;
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signal current_state : SPC_STATE;
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begin
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begin
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ATN_out <= '0' when current_state = ST_WAIT_DAC else ATN_in;
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ATN_out <= '0' when current_state = ST_WAIT_DAC else ATN_in;
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output_valid_out <= '0' when current_state = ST_WAIT_DAC else output_valid_in;
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output_valid_out <= '0' when current_state = ST_WAIT_DAC else output_valid_in;
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stb_received <= '1' when current_state = ST_WAIT_REC_STB_0 else '0';
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stb_received <= '1' when current_state = ST_WAIT_REC_STB_0 else '0';
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process (clk, reset) begin
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process (clk, reset) begin
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if reset = '1' then
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if reset = '1' then
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current_state <= ST_IDLE;
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current_state <= ST_IDLE;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case current_state is
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case current_state is
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when ST_IDLE =>
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when ST_IDLE =>
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if rec_stb='1' then
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if rec_stb='1' then
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current_state <= ST_WAIT_DAC;
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current_state <= ST_WAIT_DAC;
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end if;
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end if;
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when ST_WAIT_DAC =>
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when ST_WAIT_DAC =>
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if DAC='1' then
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if DAC='1' then
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current_state <= ST_WAIT_REC_STB_0;
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current_state <= ST_WAIT_REC_STB_0;
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elsif rec_stb='0' then
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elsif rec_stb='0' then
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current_state <= ST_IDLE;
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current_state <= ST_IDLE;
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end if;
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end if;
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when ST_WAIT_REC_STB_0 =>
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when ST_WAIT_REC_STB_0 =>
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if rec_stb='0' then
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if rec_stb='0' then
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current_state <= ST_IDLE;
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current_state <= ST_IDLE;
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end if;
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end if;
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when others =>
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when others =>
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current_state <= ST_IDLE;
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current_state <= ST_IDLE;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end arch;
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end arch;
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