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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: EventReg
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-- Entity: EventReg
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-- Date:2011-11-11
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-- Date:2011-11-11
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-- Author: Administrator
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.helperComponents.all;
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use work.helperComponents.all;
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entity EventReg is
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entity EventReg is
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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strobe : in std_logic;
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strobe : in std_logic;
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data_in : in std_logic_vector (15 downto 0);
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data_in : in std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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-------------------- gpib device ---------------------
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-------------------- gpib device ---------------------
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-- device is local controlled
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-- device is local controlled
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isLocal : in std_logic;
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isLocal : in std_logic;
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-- input buffer ready
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-- input buffer ready
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in_buf_ready : in std_logic;
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in_buf_ready : in std_logic;
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-- output buffer ready
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-- output buffer ready
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out_buf_ready : in std_logic;
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out_buf_ready : in std_logic;
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-- clear device (DC)
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-- clear device (DC)
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clr : in std_logic;
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clr : in std_logic;
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-- trigger device (DT)
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-- trigger device (DT)
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trg : in std_logic;
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trg : in std_logic;
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-- addressed to talk(L or LE)
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-- addressed to talk(L or LE)
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att : in std_logic;
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att : in std_logic;
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-- addressed to listen (T or TE)
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-- addressed to listen (T or TE)
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atl : in std_logic;
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atl : in std_logic;
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-- seriall poll active
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-- seriall poll active
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spa : in std_logic;
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spa : in std_logic;
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-------------------- gpib controller ---------------------
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-------------------- gpib controller ---------------------
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-- controller write commands
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-- controller write commands
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cwrc : in std_logic;
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cwrc : in std_logic;
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-- controller write data
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-- controller write data
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cwrd : in std_logic;
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cwrd : in std_logic;
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-- service requested
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-- service requested
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srq : in std_logic;
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srq : in std_logic;
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-- parallel poll ready
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-- parallel poll ready
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ppr : in std_logic;
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ppr : in std_logic;
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-- stb received
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-- stb received
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stb_received : in std_logic;
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stb_received : in std_logic;
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REN : in std_logic;
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REN : in std_logic;
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ATN : in std_logic;
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ATN : in std_logic;
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IFC : in std_logic
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IFC : in std_logic
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);
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);
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end EventReg;
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end EventReg;
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architecture arch of EventReg is
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architecture arch of EventReg is
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signal i_clr : std_logic;
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signal i_clr : std_logic;
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signal i_trg : std_logic;
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signal i_trg : std_logic;
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signal i_srq : std_logic;
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signal i_srq : std_logic;
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signal clr_app : std_logic;
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signal clr_app : std_logic;
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signal trg_app : std_logic;
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signal trg_app : std_logic;
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signal srq_app : std_logic;
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signal srq_app : std_logic;
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signal t_clr_in, t_clr_out : std_logic;
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signal t_clr_in, t_clr_out : std_logic;
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signal t_trg_in, t_trg_out : std_logic;
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signal t_trg_in, t_trg_out : std_logic;
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signal t_srq_in, t_srq_out : std_logic;
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signal t_srq_in, t_srq_out : std_logic;
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begin
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begin
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data_out(0) <= isLocal;
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data_out(0) <= isLocal;
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data_out(1) <= in_buf_ready;
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data_out(1) <= in_buf_ready;
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data_out(2) <= out_buf_ready;
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data_out(2) <= out_buf_ready;
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data_out(3) <= i_clr;
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data_out(3) <= i_clr;
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data_out(4) <= i_trg;
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data_out(4) <= i_trg;
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data_out(5) <= att;
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data_out(5) <= att;
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data_out(6) <= atl;
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data_out(6) <= atl;
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data_out(7) <= spa;
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data_out(7) <= spa;
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data_out(8) <= cwrc;
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data_out(8) <= cwrc;
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data_out(9) <= cwrd;
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data_out(9) <= cwrd;
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data_out(10) <= i_srq;
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data_out(10) <= i_srq;
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data_out(11) <= ppr;
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data_out(11) <= ppr;
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data_out(12) <= stb_received;
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data_out(12) <= stb_received;
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data_out(13) <= REN;
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data_out(13) <= REN;
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data_out(14) <= ATN;
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data_out(14) <= ATN;
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data_out(15) <= IFC;
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data_out(15) <= IFC;
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process (reset, strobe) begin
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process (reset, strobe) begin
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if reset = '1' then
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if reset = '1' then
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t_clr_in <= '0';
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t_clr_in <= '0';
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t_trg_in <= '0';
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t_trg_in <= '0';
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t_srq_in <= '0';
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t_srq_in <= '0';
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elsif rising_edge(strobe) then
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elsif rising_edge(strobe) then
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if data_in(3) = '0' then
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if data_in(3) = '0' then
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t_clr_in <= not t_clr_out;
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t_clr_in <= not t_clr_out;
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elsif data_in(4) = '0' then
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elsif data_in(4) = '0' then
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t_trg_in <= not t_trg_out;
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t_trg_in <= not t_trg_out;
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elsif data_in(10) = '0' then
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elsif data_in(10) = '0' then
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t_srq_in <= not t_srq_out;
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t_srq_in <= not t_srq_out;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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EVM1: EventMem port map (
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EVM1: EventMem port map (
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reset => reset, occured => clr, approved => clr_app,
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reset => reset, occured => clr, approved => clr_app,
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output => i_clr
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output => i_clr
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);
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);
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SPG1: SinglePulseGenerator generic map (WIDTH => 1) port map(
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SPG1: SinglePulseGenerator generic map (WIDTH => 1) port map(
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reset => reset, clk => clk,
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reset => reset, clk => clk,
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t_in => t_clr_in, t_out => t_clr_out,
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t_in => t_clr_in, t_out => t_clr_out,
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pulse => clr_app
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pulse => clr_app
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);
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);
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EVM2: EventMem port map (
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EVM2: EventMem port map (
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reset => reset, occured => trg, approved => trg_app,
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reset => reset, occured => trg, approved => trg_app,
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output => i_trg
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output => i_trg
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);
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);
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SPG2: SinglePulseGenerator generic map (WIDTH => 1) port map(
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SPG2: SinglePulseGenerator generic map (WIDTH => 1) port map(
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reset => reset, clk => clk,
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reset => reset, clk => clk,
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t_in => t_trg_in, t_out => t_trg_out,
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t_in => t_trg_in, t_out => t_trg_out,
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pulse => trg_app
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pulse => trg_app
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);
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);
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EVM3: EventMem port map (
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EVM3: EventMem port map (
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reset => reset, occured => srq, approved => srq_app,
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reset => reset, occured => srq, approved => srq_app,
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output => i_srq
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output => i_srq
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);
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);
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SPG3: SinglePulseGenerator generic map (WIDTH => 1) port map(
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SPG3: SinglePulseGenerator generic map (WIDTH => 1) port map(
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reset => reset, clk => clk,
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reset => reset, clk => clk,
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t_in => t_srq_in, t_out => t_srq_out,
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t_in => t_srq_in, t_out => t_srq_out,
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pulse => srq_app
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pulse => srq_app
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);
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);
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end arch;
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end arch;
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